From: lkcl <lkcl@web>
Date: Wed, 4 May 2022 11:12:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2483
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11d520713603703a2c0ccc1404d20642aa6dcb08;p=libreriscv.git

---

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index 470bcf1f1..866ed6456 100644
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -187,6 +187,8 @@ For 8,16,32,64, resulting in 8,16,32,64,128.
 
 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 
+(Now added `madded` which is twin-half 64x64->HI64/LO64 in [[sv/biginteger]])
+
 ## vec_rl - rotate left
 
     (a << x) | (a >> (WIDTH - x))