From: Andrea Pellegrini <andrea.pellegrini@gmail.com>
Date: Tue, 22 Jan 2013 06:13:28 +0000 (-0600)
Subject: o3 cpu: fix zero reg problem
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11d5ffa108983d5d9742f0aad23f80c691f285ee;p=gem5.git

o3 cpu: fix zero reg problem
There was an issue w/ the rename logic, which would assign a previous physical
register to the ZeroReg architectural register in x86.  This issue was giving
problems for instructions squashed in threads w/ ID different from 0,
sometimes allowing non-mispredicted instructions to obtain a value different
from zero when reading the zeroReg.
---

diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 8508071b4..57caa76be 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -158,6 +158,7 @@ SimpleRenameMap::rename(RegIndex arch_reg)
         } else {
             // Otherwise return the zero register so nothing bad happens.
             renamed_reg = intZeroReg;
+            prev_reg = intZeroReg;
         }
     } else if (arch_reg < numLogicalRegs) {
         // Record the current physical register that is renamed to the