From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sat, 9 Apr 2022 20:01:28 +0000 (-0500)
Subject: Avoid timing violation on ECP5 PHY PAUSE signal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11d72971fc1656daa05abfa7ff33f697eb3d629f;p=gram.git

Avoid timing violation on ECP5 PHY PAUSE signal
---

diff --git a/examples/headless/main.c b/examples/headless/main.c
index 37d22bd..43bfab7 100644
--- a/examples/headless/main.c
+++ b/examples/headless/main.c
@@ -131,10 +131,10 @@ int main(int argc, char *argv[]) {
 #if 1
 	struct gramProfile profile = {
 		.mode_registers = {
-			0xb20, 0x806, 0x200, 0x0
+			0xb30, 0x806, 0x200, 0x0
 		},
-		.rdly_p0 = 2,
-		.rdly_p1 = 2,
+		.rdly_p0 = 5,
+		.rdly_p1 = 5,
 	};
 #endif
 #if 0
@@ -167,7 +167,7 @@ int main(int argc, char *argv[]) {
 	gram_init(&ctx, &profile, (void*)ddr_base, (void*)0x00009000, (void*)0x00008000);
 	printf("done\n");
 
-#if 0
+#if 1
 	printf("Rdly\np0: ");
 	for (size_t i = 0; i < 8; i++) {
 		profile2.rdly_p0 = i;
@@ -201,7 +201,9 @@ int main(int argc, char *argv[]) {
 		fflush(stdout);
 	}
 	printf("\n");
+#endif
 
+#if 0
         printf("Auto calibrating... ");
         res = gram_generate_calibration(&ctx, &profile2);
         if (res != GRAM_ERR_NONE) {
diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 32a6792..007c143 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -101,10 +101,28 @@ class _DQSBUFMSettingManager(Elaboratable):
             with m.State("Idle"):
                 with m.If(self.rdly_csr.w_stb):
                     m.d.sync += self.pause.eq(1)
-                    m.next = "RdlyUpdateRequested"
+                    m.next = "RdlyUpdateRequestedDelay1"
+
+            with m.State("RdlyUpdateRequestedDelay1"):
+                m.next = "RdlyUpdateRequestedDelay2"
+
+            with m.State("RdlyUpdateRequestedDelay2"):
+                m.next = "RdlyUpdateRequestedDelay3"
+
+            with m.State("RdlyUpdateRequestedDelay3"):
+                m.next = "RdlyUpdateRequested"
 
             with m.State("RdlyUpdateRequested"):
                 m.d.sync += self.readclksel.eq(self.rdly_csr.w_data)
+                m.next = "ResetPauseDelay1"
+
+            with m.State("ResetPauseDelay1"):
+                m.next = "ResetPauseDelay2"
+
+            with m.State("ResetPauseDelay2"):
+                m.next = "ResetPauseDelay3"
+
+            with m.State("ResetPauseDelay3"):
                 m.next = "ResetPause"
 
             with m.State("ResetPause"):
diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c
index 17e18da..8049a07 100644
--- a/libgram/src/dfii.c
+++ b/libgram/src/dfii.c
@@ -56,6 +56,12 @@ static void dfii_set_mr(const struct gramCtx *ctx, uint8_t mr, uint16_t val) {
 
 #define MR0_DLL_RESET (1 << 8)
 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile) {
+	/* Assert reset */
+	dfii_set_p0_address(ctx, 0x0);
+	dfii_set_p0_baddress(ctx, 0);
+	dfii_setcontrol(ctx, 0);
+	cdelay(50000);
+
 	/* Release reset */
 	dfii_set_p0_address(ctx, 0x0);
 	dfii_set_p0_baddress(ctx, 0);