From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 13 May 2020 17:51:13 +0000 (-0400)
Subject: Somewhat working now?
X-Git-Tag: div_pipeline~1260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11e1f9d2fd224050561590aa815bff9dd20becc6;p=soc.git

Somewhat working now?
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index bdc66574..ad1ae63a 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -144,6 +144,13 @@ class ALUTestCase(FHDLTestCase):
         initial_sprs[special_sprs['XER']] = xer
         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 
+    def test_cmp(self):
+        lst = ["cmp cr2, 1, 6, 7"]
+        initial_regs = [0] * 32
+        initial_regs[6] = random.randint(0, (1<<64)-1)
+        initial_regs[7] = random.randint(0, (1<<64)-1)
+        self.run_tst_program(Program(lst), initial_regs, {})
+
     def test_ilang(self):
         rec = CompALUOpSubset()
 
diff --git a/src/soc/shift_rot/main_stage.py b/src/soc/shift_rot/main_stage.py
index aa2b79a5..e0b453b4 100644
--- a/src/soc/shift_rot/main_stage.py
+++ b/src/soc/shift_rot/main_stage.py
@@ -57,6 +57,10 @@ class ShiftRotMainStage(PipeModBase):
                 comb += [rotator.right_shift.eq(1),
                         rotator.clear_left.eq(0),
                         rotator.clear_right.eq(0)]
+            with m.Case(InternalOp.OP_RLC):
+                comb += [rotator.right_shift.eq(0),
+                        rotator.clear_left.eq(1),
+                        rotator.clear_right.eq(1)]