From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 26 Aug 2016 04:36:09 +0000 (-0700)
Subject: Allow reads from tdrdata registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11ef82c72623aa8649d80b3efbb629f73ad039cb;p=riscv-isa-sim.git

Allow reads from tdrdata registers
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0a7912b..c3c66b7 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -482,6 +482,9 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_TDRSELECT: return 0;
+    case CSR_TDRDATA1: return 0;
+    case CSR_TDRDATA2: return 0;
+    case CSR_TDRDATA3: return 0;
     case CSR_DCSR:
       {
         uint32_t v = 0;