From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Jul 2020 19:19:48 +0000 (+0100)
Subject: improve debug for test_sim.py
X-Git-Tag: div_pipeline~162^2~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1214dfe6b94026030b0a945bca23e86db9861ac8;p=soc.git

improve debug for test_sim.py
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index f6a52fc9..e6b09667 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -294,7 +294,8 @@ class DecoderBase:
         for reg in regs:
             qemu_val = qemu.get_register(reg)
             sim_val = sim.gpr(reg).value
-            self.assertEqual(qemu_val, sim_val)
+            self.assertEqual(qemu_val, sim_val,
+                             "expect %x got %x" % (qemu_val, sim_val))
 
 
 class DecoderTestCase(DecoderBase, GeneralTestCases):