From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 30 Apr 2018 22:46:26 +0000 (+0200)
Subject: soc/intergration/soc_core: don't delete uart/timer0 interrupts
X-Git-Tag: 24jan2021_ls180~1713
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=121eaba722e0b0b732003473630362dba4d48182;p=litex.git

soc/intergration/soc_core: don't delete uart/timer0 interrupts
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 5ef85397..c439f55d 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -146,8 +146,8 @@ class SoCCore(Module):
             else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = uart.UART(self.uart_phy)
-        else:
-            del self.soc_interrupt_map["uart"]
+        #else:
+        #    del self.soc_interrupt_map["uart"]
 
         if ident:
             if ident_version:
@@ -158,8 +158,8 @@ class SoCCore(Module):
 
         if with_timer:
             self.submodules.timer0 = timer.Timer()
-        else:
-            del self.soc_interrupt_map["timer0"]
+        #else:
+        #    del self.soc_interrupt_map["timer0"]
 
         # Invert the interrupt map.
         interrupt_rmap = {}