From: Tobias Platen <tplaten@posteo.de>
Date: Tue, 9 Jun 2020 12:00:50 +0000 (+0200)
Subject: fixes for DualPortSplitter
X-Git-Tag: div_pipeline~451
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12297566322355ce5fed2e2a5460bea54f69e79e;p=soc.git

fixes for DualPortSplitter
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 3b63b4c5..09f277fd 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -139,14 +139,16 @@ class DualPortSplitter(Elaboratable):
     a binary number (accepting values 1-16).
     """
     def __init__(self):
-        self.outp = []
-        self.outp[0] = PortInterface(name="outp_0")
-        self.outp[1] = PortInterface(name="outp_1")
-        self.inp     = PortInterface(name="inp")
+        self.outp = [PortInterface(name="outp_0"),
+                     PortInterface(name="outp_1")]
+        self.inp  = PortInterface(name="inp")
+        print(self.outp)
 
     def elaborate(self, platform):
-        splitter = LDSTSplitter(64, 48, 4)
-
+        m = Module()
+        comb = m.d.comb
+        #TODO splitter = LDSTSplitter(64, 48, 4)
+        return m
 
 class DataMergerRecord(Record):
     """
@@ -160,11 +162,10 @@ class DataMergerRecord(Record):
 
         Record.__init__(self, Layout(layout), name=name)
 
-        self.data.reset_less = True
-        self.en.reset_less = True
-
+        #FIXME: make resetless
 
 # TODO: formal verification
+
 class DataMerger(Elaboratable):
     """DataMerger
 
@@ -307,19 +308,11 @@ class L0CacheBuffer(Elaboratable):
     def __init__(self, n_units, mem, regwid=64, addrwid=48):
         self.n_units = n_units
         self.mem = mem
-        self.regwid = regwid
-        self.addrwid = addrwid
         ul = []
         for i in range(n_units):
             ul.append(LDSTPort(i, regwid, addrwid))
         self.dports = Array(ul)
 
-    def truncaddr(self, addr):
-        """truncates the address to the top bits of the memory granularity
-        """
-        nbits = log2_int(self.mem.regwid)
-        return addr[nbits:]
-
     def elaborate(self, platform):
         m = Module()
         comb, sync = m.d.comb, m.d.sync
@@ -554,7 +547,6 @@ def l0_cache_ldst(dut):
     assert data == result, "data %x != %x" % (result, data)
     assert data2 == result2, "data2 %x != %x" % (result2, data2)
 
-
 def data_merger_merge(dut):
     print("data_merger")
     #starting with all inputs zero
@@ -577,7 +569,6 @@ def data_merger_merge(dut):
     assert en == 0xff
     yield
 
-
 def test_l0_cache():
 
     dut = TstL0CacheBuffer(regwid=64)
@@ -598,7 +589,17 @@ def test_data_merger():
     run_simulation(dut, data_merger_merge(dut),
                    vcd_name='test_data_merger.vcd')
 
+def test_dual_port_splitter():
+
+    dut = DualPortSplitter()
+    #vl = rtlil.convert(dut, ports=dut.ports())
+    #with open("test_data_merger.il", "w") as f:
+    #    f.write(vl)
+
+    run_simulation(dut, data_merger_merge(dut),
+                   vcd_name='test_dual_port_splitter.vcd')
 
 if __name__ == '__main__':
-    test_l0_cache()
-    test_data_merger()
+    #test_l0_cache()
+    #test_data_merger()
+    test_dual_port_splitter()