From: Marek Olšák Date: Tue, 17 Mar 2015 13:46:04 +0000 (+0100) Subject: radeonsi: add support for ARB_texture_view X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12321966aec5e635c51208f409737dd1ddc3c883;p=mesa.git radeonsi: add support for ARB_texture_view All tests pass. We don't need to do much - just set CUBE if the view target is CUBE or CUBE_ARRAY, otherwise set the resource target. The reason this can be so simple is that texture instructions have a greater effect on the target than the sampler view. Thanks Glenn for the piglit test. Reviewed-by: Michel Dänzer --- diff --git a/docs/GL3.txt b/docs/GL3.txt index 6503e2ab1da..167321676df 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -169,7 +169,7 @@ GL 4.3, GLSL 4.30: GL_ARB_texture_buffer_range DONE (nv50, nvc0, i965, r600, radeonsi, llvmpipe) GL_ARB_texture_query_levels DONE (all drivers that support GLSL 1.30) GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample) - GL_ARB_texture_view DONE (i965, nv50, nvc0, llvmpipe, softpipe) + GL_ARB_texture_view DONE (i965, nv50, nvc0, radeonsi, llvmpipe, softpipe) GL_ARB_vertex_attrib_binding DONE (all drivers) diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html index dcf425e4c68..d3dbe9dda13 100644 --- a/docs/relnotes/11.1.0.html +++ b/docs/relnotes/11.1.0.html @@ -51,6 +51,7 @@ Note: some of the new features are only available with certain drivers.
  • GL_ARB_shader_texture_image_samples on i965, nv50, nvc0, r600, radeonsi
  • GL_ARB_texture_barrier / GL_NV_texture_barrier on i965
  • GL_ARB_texture_query_lod on softpipe
    • +
  • GL_ARB_texture_view on radeonsi
  • EGL_KHR_create_context on softpipe, llvmpipe
  • EGL_KHR_gl_colorspace on softpipe, llvmpipe
    • diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 53c80dba602..6be78afe4a9 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -294,6 +294,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_FLOAT_LINEAR: case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: case PIPE_CAP_DEPTH_BOUNDS_TEST: + case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_TGSI_TXQS: @@ -335,7 +336,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: - case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_VERTEXID_NOBASE: return 0; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index e6475364f98..2e77a3605a6 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1535,9 +1535,14 @@ static unsigned si_tex_compare(unsigned compare) } } -static unsigned si_tex_dim(unsigned dim, unsigned nr_samples) +static unsigned si_tex_dim(unsigned res_target, unsigned view_target, + unsigned nr_samples) { - switch (dim) { + if (view_target == PIPE_TEXTURE_CUBE || + view_target == PIPE_TEXTURE_CUBE_ARRAY) + res_target = view_target; + + switch (res_target) { default: case PIPE_TEXTURE_1D: return V_008F1C_SQ_RSRC_IMG_1D; @@ -2391,6 +2396,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx, struct radeon_surf_level *surflevel; int first_non_void; uint64_t va; + unsigned last_layer = state->u.tex.last_layer; if (view == NULL) return NULL; @@ -2596,6 +2602,13 @@ si_create_sampler_view_custom(struct pipe_context *ctx, } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) depth = texture->array_size / 6; + /* This is not needed if state trackers set last_layer correctly. */ + if (state->target == PIPE_TEXTURE_1D || + state->target == PIPE_TEXTURE_2D || + state->target == PIPE_TEXTURE_RECT || + state->target == PIPE_TEXTURE_CUBE) + last_layer = state->u.tex.first_layer; + va = tmp->resource.gpu_address + surflevel[base_level].offset; view->state[0] = va >> 8; @@ -2615,10 +2628,11 @@ si_create_sampler_view_custom(struct pipe_context *ctx, last_level) | S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) | S_008F1C_POW2_PAD(texture->last_level > 0) | - S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples))); + S_008F1C_TYPE(si_tex_dim(texture->target, state->target, + texture->nr_samples))); view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | - S_008F24_LAST_ARRAY(state->u.tex.last_layer)); + S_008F24_LAST_ARRAY(last_layer)); view->state[6] = 0; view->state[7] = 0; @@ -2653,11 +2667,12 @@ si_create_sampler_view_custom(struct pipe_context *ctx, S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) | - S_008F1C_TYPE(si_tex_dim(texture->target, 0)); + S_008F1C_TYPE(si_tex_dim(texture->target, + state->target, 0)); view->fmask_state[4] = S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(tmp->fmask.pitch - 1); view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) | - S_008F24_LAST_ARRAY(state->u.tex.last_layer); + S_008F24_LAST_ARRAY(last_layer); view->fmask_state[6] = 0; view->fmask_state[7] = 0; }