From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 18:22:49 +0000 (-0700)
Subject: Add warning if synth_xilinx -abc9 with family != xc7
X-Git-Tag: working-ls180~1237^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1237a4c11679685808a677593e261e21b950749a;p=yosys.git

Add warning if synth_xilinx -abc9 with family != xc7
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index fab070882..7dbd98055 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -302,6 +302,8 @@ struct SynthXilinxPass : public ScriptPass
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 			else if (abc9) {
+				if (family != "xc7")
+					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 				else