From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 23 Jun 2015 14:15:28 +0000 (+0200)
Subject: liteeth/example_designs: use new Keep SynthesisDirective
X-Git-Tag: 24jan2021_ls180~2222
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=125432b5b69e46ed456f0cdc8fbd4b61a3b0c735;p=litex.git

liteeth/example_designs: use new Keep SynthesisDirective
---

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index fe48ede3..f5dbe912 100644
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -1,6 +1,7 @@
 from migen.bus import wishbone
 from migen.bank.description import *
 from migen.genlib.io import CRG
+from migen.fhdl.specials import Keep
 from mibuild.xilinx.vivado import XilinxVivadoToolchain
 
 from misoclib.soc import SoC
@@ -45,6 +46,11 @@ class BaseSoC(SoC, AutoCSR):
         self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
 
         if isinstance(platform.toolchain, XilinxVivadoToolchain):
+            self.specials += [
+                Keep(self.crg.cd_sys.clk),
+                Keep(self.phy.crg.cd_eth_rx.clk),
+                Keep(self.phy.crg.cd_eth_tx.clk)
+            ]
             platform.add_platform_command("""
 create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
 create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]