From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 May 2018 12:26:51 +0000 (+0100)
Subject: add slide
X-Git-Tag: convert-csv-opcode-to-binary~5336
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1267fb1862dc47092fcd29e284c7a44f5aa45538;p=libreriscv.git

add slide
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 49cea203f..e76e62ea4 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -318,7 +318,7 @@ for (int i = 0; i < VL; ++i)
 
   \begin{itemize}
    \item Again: SIMD slightly more complex
-   \item rs2 vectorised taken to implicitly indicate LD.X
+   \item rs2 vectorised taken to implicitly indicate VLD.X
   \end{itemize}
 \end{frame}