From: Kenneth Graunke Date: Fri, 16 Jan 2015 08:53:53 +0000 (-0800) Subject: i965: Fix some oddities in FB_WRITE register width and execution size. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=127c9724924f9d93652540a9f3ff8306bb1aacd4;p=mesa.git i965: Fix some oddities in FB_WRITE register width and execution size. Previously, we generated this for FB writes in SIMD16 mode: load_payload(16) vgrf5@8+0.0:F, vgrf1:F, vgrf2:F, vgrf3:F, vgrf4:F fb_write(8) (null):UD, vgrf5@8+0.0:F 1sthalf The LOAD_PAYLOAD's destination had its register width set to 8, and the FB_WRITE had its execution size set to 8. This seems wrong, and while it probably doesn't affect anything, we should fix it. Signed-off-by: Kenneth Graunke Reviewed-by: Matt Turner Reviewed-by: Jason Ekstrand --- diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 4f899748e9e..8aafbef7230 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3460,6 +3460,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1, fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F); load = emit(LOAD_PAYLOAD(payload, sources, length)); payload.reg = virtual_grf_alloc(load->regs_written); + payload.width = dispatch_width; load->dst = payload; write = emit(FS_OPCODE_FB_WRITE, reg_undef, payload); write->base_mrf = -1; @@ -3468,6 +3469,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1, load = emit(LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F), sources, length)); write = emit(FS_OPCODE_FB_WRITE); + write->exec_size = dispatch_width; write->base_mrf = 1; }