From: Tim Newsome <tim@sifive.com>
Date: Fri, 3 Jun 2016 20:08:09 +0000 (-0700)
Subject: DCSR cause was moved, bug debug ROM wasn't updated
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=127cf78387447aba8f6bd19783a0c66ae5f3791a;p=riscv-isa-sim.git

DCSR cause was moved, bug debug ROM wasn't updated

As a result Debug ROM would always take the spontaneous halt code path.
This didn't hurt spike since (so far?) the spike debug handler doesn't
attempt to do anything quick while code is running. But now the ROM is
more correct.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 457104f..9e83098 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -72,9 +72,9 @@ _entry:
 
         # Check why we're here
         csrr    s0, CSR_DCSR
-        # cause is in bits 2:0 of dcsr
+        # cause is in bits 8:6 of dcsr
         andi    s0, s0, DCSR_CAUSE
-        addi    s0, s0, -DCSR_CAUSE_DEBUGINT
+        addi    s0, s0, -(DCSR_CAUSE_DEBUGINT<<6)
         bnez    s0, spontaneous_halt
 
 jdebugram:
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index bbd7f23..a929a27 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -8,7 +8,7 @@ static const unsigned char debug_rom_raw[] = {
   0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00,
   0x6f, 0x00, 0x80, 0x05, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
   0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
-  0x13, 0x04, 0xd4, 0xff, 0x63, 0x18, 0x04, 0x02, 0x0f, 0x10, 0x00, 0x00,
+  0x13, 0x04, 0x04, 0xf4, 0x63, 0x18, 0x04, 0x02, 0x0f, 0x10, 0x00, 0x00,
   0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42,
   0x67, 0x00, 0x00, 0x40, 0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00,
   0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40, 0x13, 0x00, 0x00, 0x00,