From: Andrew Cagney Date: Fri, 30 May 1997 07:25:13 +0000 (+0000) Subject: Add assembler information to igen input files. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=128b51546e6f158723ce2d1fe6fc87bda78d9583;p=binutils-gdb.git Add assembler information to igen input files. --- diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index 62aecf21799..ba68c04b4b8 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,20 @@ +Thu May 29 14:02:40 1997 Andrew Cagney + + * misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1, + tic80_trace_fpu2i): Pass in function prefix. + (tic80_trace_ldst): Rewrite so it calls print_one_insn directly. + + * Makefile.in (SIM_OBJS): Include sim-watch.o module. + + * sim-main.h (WITH_WATCHPOINTS): Enable watchpoints. + + * ic (bitnum): Compute bitnum from BITNUM. + * insn (bbo, bbz): Use. + + * insn: Convert long immediate instructions to igen long immediate + form. + * insn: Add disasembler information. + Thu May 29 12:09:13 1997 Andrew Cagney * alu.h (IMEM_IMMED): New macro, fetch 32bit immediate operand N. diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in index 9075ac7ec98..605418f5d75 100644 --- a/sim/tic80/Makefile.in +++ b/sim/tic80/Makefile.in @@ -27,7 +27,8 @@ SIM_OBJS = sim-endian.o sim-bits.o sim-config.o \ sim-run.o \ sim-resume.o \ sim-stop.o \ - sim-reason.o + sim-reason.o \ + sim-watch.o # List of extra dependencies. # Generally this consists of simulator specific files included by sim-main.h. diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h index d3d14b69ea3..ca2d3275dc8 100644 --- a/sim/tic80/cpu.h +++ b/sim/tic80/cpu.h @@ -172,7 +172,7 @@ extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32)); extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32)); extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32)); -extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32)); +extern void tic80_trace_ldst PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, int, int, int, unsigned32, unsigned32, unsigned32)); #define TRACE_ALU3(indx, result, input1, input2) \ do { \ @@ -202,31 +202,35 @@ do { \ } \ } while (0) -#define TRACE_FPU3(indx, result, input1, input2) \ +#define TRACE_FPU3(result, input1, input2) \ do { \ if (TRACE_FPU_P (CPU)) { \ - tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2); \ + tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \ + result, input1, input2); \ } \ } while (0) -#define TRACE_FPU2(indx, result, input) \ +#define TRACE_FPU2(result, input) \ do { \ if (TRACE_FPU_P (CPU)) { \ - tic80_trace_fpu2 (SD, CPU, cia, indx, result, input); \ + tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \ + result, input); \ } \ } while (0) -#define TRACE_FPU1(indx, result) \ +#define TRACE_FPU1(result) \ do { \ if (TRACE_FPU_P (CPU)) { \ - tic80_trace_fpu1 (SD, CPU, cia, indx, result); \ + tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \ + result); \ } \ } while (0) -#define TRACE_FPU2I(indx, result, input1, input2) \ +#define TRACE_FPU2I(result, input1, input2) \ do { \ if (TRACE_FPU_P (CPU)) { \ - tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2); \ + tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \ + result, input1, input2); \ } \ } while (0) @@ -284,35 +288,35 @@ do { \ } \ } while (0) -#define TRACE_LD(indx, result, m, s, addr1, addr2) \ +#define TRACE_LD(result, m, s, addr1, addr2) \ do { \ if (TRACE_MEMORY_P (CPU)) { \ - trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ - itable[indx].line_nr, "memory", \ - tic80_trace_ldst (indx, 0, m, s, result, \ - addr1, addr2)); \ + tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \ + 0, m, s, result, addr1, addr2); \ } \ } while (0) -#define TRACE_ST(indx, value, m, s, addr1, addr2) \ +#define TRACE_ST(value, m, s, addr1, addr2) \ do { \ if (TRACE_MEMORY_P (CPU)) { \ - trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ - itable[indx].line_nr, "memory", \ - tic80_trace_ldst (indx, 1, m, s, value, \ - addr1, addr2)); \ + tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \ + 1, m, s, value, addr1, addr2); \ } \ } while (0) #else #define TRACE_ALU3(indx, result, input1, input2) #define TRACE_ALU2(indx, result, input) +#define TRACE_FPU3(result, input1, input2) +#define TRACE_FPU2(result, input) +#define TRACE_FPU1(result) +#define TRACE_FPU2I(result, input1, input2) #define TRACE_NOP(indx) #define TRACE_SINK1(indx, input) #define TRACE_SINK2(indx, input1, input2) #define TRACE_SINK3(indx, input1, input2, input3) #define TRACE_COND_BR(indx, jump_p, cond, target) #define TRACE_UCOND_BR(indx, target) -#define TRACE_LD(indx, m, s, result, addr1, addr2) -#define TRACE_ST(indx, m, s, value, addr1, addr2) +#define TRACE_LD(m, s, result, addr1, addr2) +#define TRACE_ST(m, s, value, addr1, addr2) #endif diff --git a/sim/tic80/ic b/sim/tic80/ic index 54a2550536d..17067fbaa4f 100644 --- a/sim/tic80/ic +++ b/sim/tic80/ic @@ -40,6 +40,8 @@ compute:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate # compute:BITNUM:BITNUM: compute:Code:Code: +compute:BITNUM:bitnum:int:(~BITNUM) & 0x1f + # compute:SignedOffset:SignedOffset: compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14) diff --git a/sim/tic80/insns b/sim/tic80/insns index a3aceaea505..0da69a60f98 100644 --- a/sim/tic80/insns +++ b/sim/tic80/insns @@ -58,11 +58,13 @@ void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2 TRACE_ALU3 (MY_INDEX, result, source1, source2); /* FIXME - a signed add may cause an exception */ 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i +"add , r, r" do_add (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r +"add r, r, r" do_add (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./+LongSignedImmediate::::add l +"add 0x%08lx, r, r" do_add (_SD, rDest, LongSignedImmediate, vSource2); @@ -73,11 +75,13 @@ void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source *rDest = result; 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i +"addu , r, r" do_addu (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r +"addu r, r, r" do_addu (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./+LongSignedImmediate::::addu l +"addu 0x%08lx, r, r" do_addu (_SD, rDest, LongSignedImmediate, vSource2); @@ -89,49 +93,56 @@ void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2 // and, and.tt 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i +"and.tt , r, r" do_and (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r +"and.tt r, r, r" do_and (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b110010001,12.1,11./+LongSignedImmediate::::and.tt l +"and.tt 0x%08lx, r, r" do_and (_SD, rDest, LongSignedImmediate, vSource2); // and.ff 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i +"and.ff , r, r" do_and (_SD, rDest, ~vSource1, ~vSource2); 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r +"and.ff r, r, r" do_and (_SD, rDest, ~vSource1, ~vSource2); -31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b110011000,12.1,11./+LongSignedImmediate::::and.ff l +"and.ff 0x%08lx, r, r" do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2); // and.ft 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i +"and.ft , r, r" do_and (_SD, rDest, ~vSource1, vSource2); 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r +"and.ft r, r, r" do_and (_SD, rDest, ~vSource1, vSource2); -31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b110010100,12.1,11./+LongSignedImmediate::::and.ft l +"and.ft 0x%08lx, r, r" do_and (_SD, rDest, ~LongSignedImmediate, vSource2); // and.tf 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i +"and.tf , r, r" do_and (_SD, rDest, vSource1, ~vSource2); 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r +"and.tf r, r, r" do_and (_SD, rDest, vSource1, ~vSource2); -31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b110010010,12.1,11./+LongSignedImmediate::::and.tf l +"and.tf 0x%08lx, r, r" do_and (_SD, rDest, LongSignedImmediate, ~vSource2); -// bbo.[a] +// bbo[.a] instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset int jump_p; address_word target = cia.ip + 4 * offset; - bitnum = (~ bitnum) & 0x1f; if (MASKED32 (source, bitnum, bitnum)) { nia = do_branch (_SD, annul, target, 0, NULL); @@ -141,20 +152,26 @@ instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsig jump_p = 0; TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); return nia; +const char *::function::str_A:int A + if (A) + return ".a"; + else + return ""; 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i - nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset); +"bbo%s , r, " + nia = do_bbo (_SD, nia, bitnum, vSource, A, vSignedOffset); 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r - nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff); -31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l - long_immediate (LongSignedImmediate); - nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate); +"bbo%s r, r, " + nia = do_bbo (_SD, nia, bitnum, vSource, A, rIndOff); +31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./+LongSignedImmediate::::bbo l +"bbo%s , r, " + nia = do_bbo (_SD, nia, bitnum, vSource, A, LongSignedImmediate); // bbz[.a] instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset int jump_p; address_word target = cia.ip + 4 * offset; - bitnum = (~ bitnum) & 0x1f; if (!MASKED32 (source, bitnum, bitnum)) { nia = do_branch (_SD, annul, target, 0, NULL); @@ -165,12 +182,14 @@ instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsig TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); return nia; 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i - nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset); +"bbz%s , r, " + nia = do_bbz (_SD, nia, bitnum, vSource, A, vSignedOffset); 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r - nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff); -31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l - long_immediate (LongSignedImmediate); - nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate); +"bbz%s r, r, " + nia = do_bbz (_SD, nia, bitnum, vSource, A, rIndOff); +31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./+LongSignedImmediate::::bbz l +"bbz%s , r, " + nia = do_bbz (_SD, nia, bitnum, vSource, A, LongSignedImmediate); // bcnd[.a] @@ -205,11 +224,13 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign TRACE_COND_BR(MY_INDEX, condition, source, target); return nia; 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i +"bcnd%s , r, " nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset); 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r +"bcnd%s r, r, " nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff); -31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l - long_immediate (LongSignedImmediate); +31.Code,26.Source,21.0b11100110,13.A,12.1,11./+LongSignedImmediate::::bcnd l +"bcnd%s , r, " nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate); @@ -234,11 +255,13 @@ sim_cia::function::do_brcr:instruction_address nia, int cr TRACE_UCOND_BR (MY_INDEX, nia.dp); return nia; 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i +"brcr CR[]" nia = do_brcr (_SD, nia, UCRN); 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r +"brcr CR[r]" nia = do_brcr (_SD, nia, UCRN); -31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l - long_immediate (UnsignedControlRegisterNumber) +31.//,27.0,26.//,21.0b110000110,12.1,11./+UnsignedControlRegisterNumber::::brcr l +"brcr CR[]" nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber); @@ -249,11 +272,13 @@ instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, TRACE_UCOND_BR (MY_INDEX, target); return nia; 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i +"bsr%s , r" nia = do_bsr (_SD, nia, rLink, A, vSignedOffset); 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r +"bsr%s r, r" nia = do_bsr (_SD, nia, rLink, A, rIndOff); -31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l - long_immediate (LongSignedImmediate); +31.Link,26./,21.0b11100000,13.A,12.1,11./+LongSignedImmediate::::bsr l +"bsr%s , r" nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate); @@ -297,11 +322,13 @@ void::function::do_cmnd:signed32 source } TRACE_SINK1 (MY_INDEX, source); 31./,21.0b0000010,14.UI::::cmnd i +"cmnd " do_cmnd (_SD, UI); 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r +"cmnd r" do_cmnd (_SD, vSource); -31./,21.0b110000010,12.1,11./::::cmnd l - long_immediate (LongUnsignedImmediate); +31./,21.0b110000010,12.1,11./+LongUnsignedImmediate::::cmnd l +"cmnd " do_cmnd (_SD, LongUnsignedImmediate); // cmp @@ -328,24 +355,32 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2 TRACE_ALU3 (MY_INDEX, field, source1, source2); *rDest = field; 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i +"cmp , r, r" do_cmp (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r +"cmp r, r, r" do_cmp (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b111010000,12.1,11./+LongSignedImmediate::::cmp l +"cmp 0x%08lx, r, r" do_cmp (_SD, rDest, LongSignedImmediate, vSource2); // dcache -31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i +const char *::function::str_F:int F + if (F) + return "f"; + else + return "c"; +31./,27.F,26.Source2,21.0b0111,17.m,16.0b00,14.SignedOffset::::dcache i +"dcache%s (r%s)" TRACE_NOP (MY_INDEX); /* NOP */ -31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r +31./,27.F,26.Source2,21.0b110111,15.m,14.0b00,12.0,11./,4.Source1::::dcache r +"dcache%s r (r%s)" TRACE_NOP (MY_INDEX); /* NOP */ -31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l - long_immediate (LongSignedImmediate); - LongSignedImmediate++; +31./,27.F,26.Source2,21.0b110111,15.m,14.0b00,12.1,11./+LongSignedImmediate::::dcache l +"dcache%s (r%s)" TRACE_NOP (MY_INDEX); /* NOP */ @@ -354,9 +389,10 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2 void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset do_ld (_SD, Dest, base, rBase, m, sz, S, offset); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r +"dld%s r%s (r%s), r" do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff); -31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l - long_immediate (LongSignedImmediateOffset); +31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dld l +"dld%s 0x%08lx%s (r%s), r" do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset); @@ -364,9 +400,10 @@ void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r +"dld.u%s r%s (r%s), r" do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff); -31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l - long_immediate (LongSignedImmediateOffset); +31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dld.u l +"dld.u%s 0x%08lx%s (r%s), r" do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset); @@ -374,9 +411,10 @@ void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset do_st (_SD, Source, base, rBase, m, sz, S, offset); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r +"dst%s r%s (r%s), r" do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff); -31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l - long_immediate (LongSignedImmediateOffset); +31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dst l +"dst%s 0x%08lx%s (r%s), r" do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset); @@ -453,14 +491,24 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD // fadd.{s|d}{s|d}{s|d} void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_add (s1, s2); - TRACE_FPU3 (MY_INDEX, ans, s1, s2); + TRACE_FPU3 (ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); +const char *::function::str_PX:int PX + switch (PX) + { + case 0: return "s"; + case 1: return "d"; + case 2: return "i"; + case 3: return "u"; + default: return "?"; + } 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r +"fadd.%s%s%s r, r, r" do_fadd (_SD, Dest, PD, get_fp_reg (_SD, Source1, vSource1, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fadd l +"fadd.%s%s%s 0x%08lx, r, r" do_fadd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), get_fp_reg (_SD, Source2, vSource2, P2)); @@ -490,13 +538,14 @@ void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2 || sim_fpu_is_ge (s1, s2)) result |= BIT32(29); } *rDest = result; - TRACE_FPU2I (MY_INDEX, result, s1, s2); + TRACE_FPU2I (result, s1, s2); 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r +"fcmp.%s%s r, r, r" do_fcmp (_SD, rDest, get_fp_reg (_SD, Source1, vSource1, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fcmp l +"fcmp.%s%s 0x%08lx, r, r" do_fcmp (_SD, rDest, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), get_fp_reg (_SD, Source2, vSource2, P2)); @@ -506,14 +555,15 @@ void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2 // fdiv.{s|d}{s|d}{s|d} void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_div (s1, s2); - TRACE_FPU3 (MY_INDEX, ans, s1, s2); + TRACE_FPU3 (ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r +"fdiv.%s%s%s r, r, r" do_fdiv (_SD, Dest, PD, get_fp_reg (_SD, Source1, vSource1, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fdiv l +"fdiv.%s%s%s 0x%08lx, r, r" do_fdiv (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), get_fp_reg (_SD, Source2, vSource2, P2)); @@ -526,96 +576,104 @@ void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2 case 2: /* signed */ { GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2); - TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2); + TRACE_FPU2I (GPR (Dest), s1, s2); break; } case 3: /* unsigned */ { GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2); - TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2); + TRACE_FPU2I (GPR (Dest), s1, s2); break; } default: { sim_fpu ans = sim_fpu_mul (s1, s2); set_fp_reg (_SD, Dest, ans, PD); - TRACE_FPU3 (MY_INDEX, ans, s1, s2); + TRACE_FPU3 (ans, s1, s2); } } 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r +"fmpy.%s%s%s r, r, r" do_fmpy (_SD, Dest, PD, get_fp_reg (_SD, Source1, vSource1, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fmpy l +"fmpy.%s%s%s 0x%08lx, r, r" do_fmpy (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -// frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u} +// frndm.{s|d|i|u}{s|d|i|u} void::function::do_frnd:int Dest, int PD, sim_fpu s1 set_fp_reg (_SD, Dest, s1, PD); - TRACE_FPU1 (MY_INDEX, s1); -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r + TRACE_FPU1 (s1); +31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r +"frndm.%s%s r, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, vSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./+SinglePrecisionFloatingPoint::f::frndm l +"frndm.%s%s 0x%08lx, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); -// frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r +// frndn.{s|d|i|u}{s|d|i|u} +31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r +"frndn.%s%s r, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, vSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./+SinglePrecisionFloatingPoint::f::frndn l +"frndn.%s%s 0x%08lx, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); -// frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r +// frndp.{s|d|i|u}{s|d|i|u} +31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r +"frndp.%s%s r, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, vSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./+SinglePrecisionFloatingPoint::f::frndp l +"frndp.%s%s 0x%08lx, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); -// frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r +// frndz.{s|d|i|u}{s|d|i|u} +31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r +"frndz.%s%s r, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, vSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./+SinglePrecisionFloatingPoint::f::frndz l +"frndz.%s%s 0x%08lx, r" do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); // fsqrt.{s|d}{s|d}{s|d} -#void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 +#void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source, unsigned32 Source2 # sim_io_error ("fsqrt"); -31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r -# do_fsqrt (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l -# do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2); +31.Dest,26./,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source::f::fsqrt r +"fsqrt.%s%s r, r" +# do_fsqrt (_SD, rDest, vSource); +31.Dest,26./,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./+SinglePrecisionFloatingPoint::f::fsqrt l +"fsqrt.%s%s 0x%08lx, r" +# do_fsqrt (_SD, rDest, SinglePrecisionFloatingPoint); // fsub.{s|d}{s|d}{s|d} void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_sub (s1, s2); - TRACE_FPU3 (MY_INDEX, ans, s1, s2); + TRACE_FPU3 (ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r +"fsub.%s%s%s r, r, r" do_fsub (_SD, Dest, PD, get_fp_reg (_SD, Source1, vSource1, P1), get_fp_reg (_SD, Source2, vSource2, P2)); -31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l - long_immediate (SinglePrecisionFloatingPoint); +31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fsub l +"fsub.%s%s%s 0x%08lx, r, r" do_fsub (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), get_fp_reg (_SD, Source2, vSource2, P2)); @@ -623,7 +681,9 @@ void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2 // illop 31./,21.0b0000000,14./::::illop +"illop" 31./,21.0b111111111,12./::::illop l +"illop" // ins - see sl.im @@ -641,11 +701,13 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, (unsigned long) nia.dp); return nia; 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i +"jsr%s , r" nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase); -31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r - nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase); -31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l - long_immediate (LongSignedImmediate); +31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.IndOff::::jsr r +"jsr%s r, r" + nia = do_jsr (_SD, nia, rLink, A, rIndOff, vBase); +31.Link,26.Base,21.0b11100010,13.A,12.1,11./+LongSignedImmediate::::jsr l +"jsr%s , r" nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase); @@ -690,13 +752,34 @@ void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int addr = -1; sim_engine_abort (SD, CPU, cia, "ld - invalid sz %d", sz); } - TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset); + TRACE_LD (GPR(Dest), m, S, base, offset); +const char *::function::str_sz:int sz + switch (sz) + { + case 0: return ".b"; + case 1: return ".h"; + case 2: return ""; + case 3: return ".d"; + default: return "?"; + } +const char *::function::str_m:int m + if (m) + return ":m"; + else + return ""; +const char *::function::str_S:int S + if (S) + return ":s"; + else + return ""; 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i +"ld%s (r%s), r" do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r +"ld%s r%s (r%s), r" do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff); -31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l - long_immediate (LongSignedImmediateOffset); +31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::ld l +"ld%s 0x%08lx%s (r%s), r" do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset); @@ -719,18 +802,21 @@ void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, i } if (m) *rBase = addr; - TRACE_LD (MY_INDEX, m, S, *rDest, base, offset); + TRACE_LD (m, S, *rDest, base, offset); 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i +"ld.u%s (r%s), r" do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r +"ld.u%s r%s (r%s), r" do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff); -31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l - long_immediate (LongSignedImmediateOffset); +31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::ld.u l +"ld.u%s 0x%08lx%s (r%s), r" do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset); // lmo 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo +"lmo r, r" int b; for (b = 0; b < 32; b++) if (vSource & BIT32 (31 - b)) @@ -750,41 +836,49 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 // or, or.tt 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i +"or.tt , r, r" do_or (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r +"or.tt r, r, r" do_or (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110010111,12.1,11./+LongUnsignedImmediate::::or.tt l +"or.tt 0x%08lx, r, r" do_or (_SD, rDest, LongUnsignedImmediate, vSource2); // or.ff 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i +"or.ff , r, r" do_or (_SD, rDest, ~vSource1, ~vSource2); 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r +"or.ff r, r, r" do_or (_SD, rDest, ~vSource1, ~vSource2); -31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110011110,12.1,11./+LongUnsignedImmediate::::or.ff l +"or.ff 0x%08lx, r, r" do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2); // or.ft 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i +"or.ft , r, r" do_or (_SD, rDest, ~vSource1, vSource2); 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r +"or.ft r, r, r" do_or (_SD, rDest, ~vSource1, vSource2); -31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110011101,12.1,11./+LongUnsignedImmediate::::or.ft l +"or.ft 0x%08lx, r, r" do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2); // or.tf 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i +"or.tf , r, r" do_or (_SD, rDest, vSource1, ~vSource2); 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r +"or.tf r, r, r" do_or (_SD, rDest, vSource1, ~vSource2); -31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110011011,12.1,11./+LongUnsignedImmediate::::or.tf l +"or.tf 0x%08lx, r, r" do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2); @@ -793,16 +887,19 @@ void::function::do_rdcr:unsigned32 Dest, int cr TRACE_SINK2 (MY_INDEX, Dest, cr); GPR (Dest) = CR (cr); 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i +"rdcr CR[], r" do_rdcr (_SD, Dest, UCRN); 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r +"rdcr CR[r], r" do_rdcr (_SD, Dest, UCRN); -31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l - long_immediate (UnsignedControlRegisterNumber); +31.Dest,26.0,21.0b110000100,12.1,11./+UnsignedControlRegisterNumber::::rdcr l +"rdcr CR[], r" do_rdcr (_SD, Dest, UnsignedControlRegisterNumber); // rmo 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo +"rmo r, r" int b; for (b = 0; b < 32; b++) if (vSource & BIT32 (b)) @@ -901,9 +998,24 @@ void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, i } TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate); +const char *::function::str_Merge:int Merge + switch (Merge) + { + case 0: return "dz"; + case 1: return "dm"; + case 2: return "ds"; + case 3: return "ez"; + case 4: return "em"; + case 5: return "es"; + case 6: return "iz"; + case 7: return "im"; + default: return "?"; + } 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i +"sl.%s , , r, r" do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate); 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r +"sl.%s r, , r, r" do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31); @@ -957,13 +1069,15 @@ void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , in } if (m) *rBase = addr; - TRACE_ST (MY_INDEX, Source, m, S, base, offset); + TRACE_ST (Source, m, S, base, offset); 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i +"st%s (r%s), r" do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r +"st%s r%s (r%s), r" do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff); -31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l - long_immediate (LongSignedImmediateOffset); +31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::st l +"st%s 0x%08lx%s (r%s), r" do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset); @@ -974,11 +1088,13 @@ void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2 ALU_END (*rDest); TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2); 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i +"sub , r, r" do_sub (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r +"sub r, r, r" do_sub (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./+LongSignedImmediate::::sub l +"sub 0x%08lx, r, r" do_sub (_SD, rDest, LongSignedImmediate, vSource2); @@ -989,11 +1105,13 @@ void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2 *rDest = result; // NOTE - the book has 15.1 which conflicts with subu. 31.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i +"subu , r, r" do_subu (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r +"subu r, r, r" do_subu (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l - long_immediate (LongSignedImmediate); +31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./+LongSignedImmediate::::subu l +"subu 0x%08lx, r, r" do_subu (_SD, rDest, LongSignedImmediate, vSource2); @@ -1017,12 +1135,14 @@ void::function::do_swcr:int Dest, signed32 source, signed32 cr GPR (Dest) = old_cr; TRACE_SINK3 (MY_INDEX, source, cr, Dest); 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i +"swcr CR[], r" do_swcr (_SD, Dest, vSource, UCRN); 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r +"swcr CR[r], r" do_swcr (_SD, Dest, vSource, UCRN); -31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l - long_immediate (LongUnsignedControlRegister); - do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister); +31.Dest,26.Source,21.0b11000010,13.1,12.1,11./+LongUnsignedControlRegisterNumber::::swcr l +"swcr CR[], r" + do_swcr (_SD, Dest, vSource, LongUnsignedControlRegisterNumber); // trap @@ -1121,11 +1241,13 @@ void::function::do_trap:unsigned32 trap_number (unsigned long) cia.ip, trap_number); } 31./,27.0,26./,21.0b0000001,14.UTN::::trap i +"trap " do_trap (_SD, UTN); 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r +"trap r" do_trap (_SD, UTN); -31./,27.0,26./,21.0b110000001,12.1,11./::::trap l - long_immediate (UTN); +31./,27.0,26./,21.0b110000001,12.1,11./+UTN::::trap l +"trap 0x%08lx" do_trap (_SD, UTN); @@ -1190,11 +1312,13 @@ void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2 TRACE_ALU3 (MY_INDEX, result, source1, source2); *rDest = result; 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i +"xnor , r, r" do_xnor (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r +"xnor r, r, r" do_xnor (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110011001,12.1,11./+LongUnsignedImmediate::::xnor l +"xnor 0x%08lx, r, r" do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2); @@ -1204,9 +1328,11 @@ void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2 TRACE_ALU3 (MY_INDEX, result, source1, source2); *rDest = result; 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i +"xor , r, r" do_xor (_SD, rDest, vSource1, vSource2); 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r +"xor r, r, r" do_xor (_SD, rDest, vSource1, vSource2); -31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l - long_immediate (LongUnsignedImmediate); +31.Dest,26.Source2,21.0b110010110,12.1,11./+LongUnsignedImmediate::::xor l +"xor 0x%08lx, r, r" do_xor (_SD, rDest, LongUnsignedImmediate, vSource2); diff --git a/sim/tic80/misc.c b/sim/tic80/misc.c index a9ce4967a50..a741c484fd0 100644 --- a/sim/tic80/misc.c +++ b/sim/tic80/misc.c @@ -411,8 +411,11 @@ tic80_trace_ucond_br (int indx, /* Trace the result of a load or store operation with 2 integer addresses and an integer output or input */ -char * -tic80_trace_ldst (int indx, +void +tic80_trace_ldst (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + int indx, int st_p, int m_p, int s_p, @@ -432,14 +435,14 @@ tic80_trace_ldst (int indx, if (s_p) strcat (name, ":s"); - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld %s 0x%.*lx/%*ld", - tic80_size_name, name, - SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1, - SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2, - (!st_p) ? "=>" : "<=", - SIZE_HEX, value, SIZE_DECIMAL, (long)(signed32)value); - - return tic80_trace_buffer; + trace_one_insn (sd, cpu, cia.ip, 1, + itable[indx].file, itable[indx].line_nr, "memory", + "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld %s 0x%.*lx/%*ld", + tic80_size_name, name, + SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1, + SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2, + (!st_p) ? "=>" : "<=", + SIZE_HEX, value, SIZE_DECIMAL, (long)(signed32)value); } #endif /* WITH_TRACE */ diff --git a/sim/tic80/sim-main.h b/sim/tic80/sim-main.h index 08818889f3e..87aef80f1ee 100644 --- a/sim/tic80/sim-main.h +++ b/sim/tic80/sim-main.h @@ -23,6 +23,7 @@ #ifndef _SIM_MAIN_H_ #define _SIM_MAIN_H_ + #include "sim-basics.h" #include @@ -40,6 +41,8 @@ typedef instruction_address sim_cia; static const sim_cia null_cia = {0}; /* Dummy */ #define NULL_CIA null_cia +#define WITH_WATCHPOINTS 1 + #include "sim-base.h" #include "alu.h"