From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 24 Oct 2023 17:16:06 +0000 (+0100)
Subject: whitespace cleanup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=128f26a582742d6225dd1f9353353d3d12ee437d;p=openpower-isa.git

whitespace cleanup
---

diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py
index 6c782409..a1f42ba2 100644
--- a/src/openpower/decoder/isa/test_syscall.py
+++ b/src/openpower/decoder/isa/test_syscall.py
@@ -70,7 +70,7 @@ class SyscallTestCase(FHDLTestCase):
         self.assertEqual(sim.msr, MSR)          # MSR changed to this by sc/trap
 
         print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1'])))
-        print("SYSCALL  MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
+        print("SYSCALL MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
         return sim
 
     def test_sc_getpid(self):