From: Doug Evans Date: Mon, 27 Apr 1998 20:10:40 +0000 (+0000) Subject: * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1294c286cbdbd3f91f75bcc1535570f6f01eda32;p=binutils-gdb.git * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 82a7d166d5c..7f49fa65d94 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -20,6 +20,7 @@ Mon Apr 27 10:33:56 1998 Doug Evans (@arch@_cgen_get_insn_operands): Change result type to void. Delete args insn_value, length. New arg fields. All callers updated. (@arch@_cgen_lookup_get_insn_operands): New function. + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. Fri Apr 24 16:07:57 1998 Alan Modra diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 27f5ea98ae8..4e5911a5490 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -36,127 +36,33 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ compiled with GCC), or switch to macros, or use something else. */ +static const char * insert_normal + PARAMS ((long, unsigned int, int, int, int, char *)); static const char * parse_insn_normal PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); static const char * insert_insn_normal PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); -/* Default insertion routine. - - ATTRS is a mask of the boolean attributes. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn (currently 8,16,32). - - The result is an error message or NULL if success. */ +/* -- assembler routines inserted here */ +/* -- asm.c */ -/* ??? This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* ??? For architectures where insns can be representable as ints, - store insn in `field' struct and add registers, etc. while parsing? */ +/* Handle '#' prefixes (i.e. skip over them). */ static const char * -insert_normal (value, attrs, start, length, shift, total_length, buffer) - long value; - unsigned int attrs; - int start; - int length; - int shift; - int total_length; - char * buffer; +parse_hash (strp, opindex, valuep) + const char **strp; + int opindex; + unsigned long *valuep; { - bfd_vma x; - static char buf[100]; - - if (shift < 0) - value <<= -shift; - else - value >>= shift; - - /* Ensure VALUE will fit. */ - if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0) - { - unsigned long max = (1 << length) - 1; - if ((unsigned long) value > max) - { - const char *err = "operand out of range (%lu not between 0 and %lu)"; - - sprintf (buf, err, value, max); - return buf; - } - } - else - { - long min = - (1 << (length - 1)); - long max = (1 << (length - 1)) - 1; - if (value < min || value > max) - { - const char *err = "operand out of range (%ld not between %ld and %ld)"; - - sprintf (buf, err, value, min, max); - return buf; - } - } - -#if 0 /*def CGEN_INT_INSN*/ - *buffer |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); -#else - switch (total_length) - { - case 8: - x = * (unsigned char *) buffer; - break; - case 16: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - x = bfd_getb16 (buffer); - else - x = bfd_getl16 (buffer); - break; - case 32: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - x = bfd_getb32 (buffer); - else - x = bfd_getl32 (buffer); - break; - default : - abort (); - } - - x |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); - - switch (total_length) - { - case 8: - * buffer = value; - break; - case 16: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb16 (x, buffer); - else - bfd_putl16 (x, buffer); - break; - case 32: - if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) - bfd_putb32 (x, buffer); - else - bfd_putl32 (x, buffer); - break; - default : - abort (); - } -#endif - + if (**strp == '#') + ++*strp; return NULL; } - -/* -- assembler routines inserted here */ -/* -- asm.c */ /* Handle shigh(), high(). */ static const char * -parse_h_hi16 (strp, opindex, valuep) +parse_hi16 (strp, opindex, valuep) const char **strp; int opindex; unsigned long *valuep; @@ -164,7 +70,6 @@ parse_h_hi16 (strp, opindex, valuep) const char *errmsg; enum cgen_parse_operand_result result_type; - /* FIXME: Need # in assembler syntax (means '#' is optional). */ if (**strp == '#') ++*strp; @@ -203,7 +108,7 @@ parse_h_hi16 (strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_h_slo16 (strp, opindex, valuep) +parse_slo16 (strp, opindex, valuep) const char **strp; int opindex; long *valuep; @@ -211,7 +116,6 @@ parse_h_slo16 (strp, opindex, valuep) const char *errmsg; enum cgen_parse_operand_result result_type; - /* FIXME: Need # in assembler syntax (means '#' is optional). */ if (**strp == '#') ++*strp; @@ -247,7 +151,7 @@ parse_h_slo16 (strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_h_ulo16 (strp, opindex, valuep) +parse_ulo16 (strp, opindex, valuep) const char **strp; int opindex; unsigned long *valuep; @@ -255,7 +159,6 @@ parse_h_ulo16 (strp, opindex, valuep) const char *errmsg; enum cgen_parse_operand_result result_type; - /* FIXME: Need # in assembler syntax (means '#' is optional). */ if (**strp == '#') ++*strp; @@ -355,14 +258,17 @@ m32r_cgen_parse_operand (opindex, strp, fields) errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, & fields->f_acc); break; /* end-sanitize-m32rx */ + case M32R_OPERAND_HASH : + errmsg = parse_hash (strp, M32R_OPERAND_HASH, &fields->f_nil); + break; case M32R_OPERAND_HI16 : - errmsg = parse_h_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16); + errmsg = parse_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16); break; case M32R_OPERAND_SLO16 : - errmsg = parse_h_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16); + errmsg = parse_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16); break; case M32R_OPERAND_ULO16 : - errmsg = parse_h_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16); + errmsg = parse_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16); break; case M32R_OPERAND_UIMM24 : errmsg = cgen_parse_address (strp, M32R_OPERAND_UIMM24, 0, NULL, & fields->f_uimm24); @@ -411,89 +317,92 @@ m32r_cgen_insert_operand (opindex, fields, buffer) switch (opindex) { case M32R_OPERAND_SR : - errmsg = insert_normal (fields->f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm8, 0|(1<f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm16, 0|(1<f_uimm4, 0|(1<f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_uimm16, 0|(1<f_imm1) - (1)); - errmsg = insert_normal (value, 0|(1<f_accd, 0|(1<f_accd, 0|(1<f_accs, 0|(1<f_accs, 0|(1<f_acc, 0|(1<f_acc, 0|(1<f_nil, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + break; case M32R_OPERAND_HI16 : - errmsg = insert_normal (fields->f_hi16, 0|(1<f_hi16, 0|(1<f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm16, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer); break; case M32R_OPERAND_ULO16 : - errmsg = insert_normal (fields->f_uimm16, 0|(1<f_uimm16, 0|(1<f_uimm24, 0|(1<f_uimm24, 0|(1<f_disp8) >> (2)); - errmsg = insert_normal (value, 0|(1<f_disp16) >> (2)); - errmsg = insert_normal (value, 0|(1<f_disp24) >> (2)); - errmsg = insert_normal (value, 0|(1< max) + { + const char *err = "operand out of range (%lu not between 0 and %lu)"; + + sprintf (buf, err, value, max); + return buf; + } + } + else + { + long min = - (1 << (length - 1)); + long max = (1 << (length - 1)) - 1; + if (value < min || value > max) + { + const char *err = "operand out of range (%ld not between %ld and %ld)"; + + sprintf (buf, err, value, min, max); + return buf; + } + } + +#if 0 /*def CGEN_INT_INSN*/ + *buffer |= ((value & ((1 << length) - 1)) + << (total_length - (start + length))); +#else + switch (total_length) + { + case 8: + x = * (unsigned char *) buffer; + break; + case 16: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + x = bfd_getb16 (buffer); + else + x = bfd_getl16 (buffer); + break; + case 32: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + x = bfd_getb32 (buffer); + else + x = bfd_getl32 (buffer); + break; + default : + abort (); + } + + x |= ((value & ((1 << length) - 1)) + << (total_length - (start + length))); + + switch (total_length) + { + case 8: + * buffer = value; + break; + case 16: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb16 (x, buffer); + else + bfd_putl16 (x, buffer); + break; + case 32: + if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG) + bfd_putb32 (x, buffer); + else + bfd_putl32 (x, buffer); + break; + default : + abort (); + } +#endif + + return NULL; +} /* Default insn parser. @@ -707,9 +719,14 @@ insert_insn_normal (insn, fields, buffer) This routine is called for each instruction to be assembled. STR points to the insn to be assembled. We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in buf. + [??? What byte order?] The result is a pointer to the insn's entry in the opcode table, or NULL if an error occured (an error message will have already been - printed). */ + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. */ const CGEN_INSN * m32r_cgen_assemble_insn (str, fields, buf, errmsg) diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index dbe52826cab..851ae828d86 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -3,7 +3,7 @@ This file is used to generate m32r-dis.c. -Copyright (C) 1996, 1997 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -46,57 +46,32 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static int print_insn PARAMS ((bfd_vma, disassemble_info *, char *, int)); +static int extract_normal + PARAMS ((PTR, cgen_insn_t, unsigned int, int, int, int, long *)); +static void print_normal + PARAMS ((PTR, long, unsigned int, unsigned long, int)); +static void print_keyword + PARAMS ((PTR, CGEN_KEYWORD *, long, unsigned int)); static int extract_insn_normal PARAMS ((const CGEN_INSN *, void *, cgen_insn_t, CGEN_FIELDS *)); static void print_insn_normal PARAMS ((void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); -/* Default extraction routine. - - ATTRS is a mask of the boolean attributes. We only need `unsigned', - but for generality we take a bitmask of all of them. */ - -static int -extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, valuep) - PTR buf_ctrl; - cgen_insn_t insn_value; - unsigned int attrs; - int start, length, shift, total_length; - long *valuep; -{ - long value; - -#ifdef CGEN_INT_INSN -#if 0 - value = ((insn_value >> (CGEN_BASE_INSN_BITSIZE - (start + length))) - & ((1 << length) - 1)); -#else - value = ((insn_value >> (total_length - (start + length))) - & ((1 << length) - 1)); -#endif - if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) - && (value & (1 << (length - 1)))) - value -= 1 << length; -#else - /* FIXME: unfinished */ -#endif - - /* This is backwards as we undo the effects of insert_normal. */ - if (shift < 0) - value >>= -shift; - else - value <<= shift; +/* -- disassembler routines inserted here */ +/* -- dis.c */ - *valuep = value; +/* Immediate values are prefixed with '#'. */ - /* FIXME: for now */ - return 1; -} +#define CGEN_PRINT_NORMAL(info, value, attrs, pc, length) \ +do { \ + if ((attrs) & (1 << CGEN_OPERAND_HASH_PREFIX)) \ + (*info->fprintf_func) (info->stream, "#"); \ +} while (0) -/* Default print handler. */ +/* Handle '#' prefixes as operands. */ static void -print_normal (dis_info, value, attrs, pc, length) +print_hash (dis_info, value, attrs, pc, length) PTR dis_info; long value; unsigned int attrs; @@ -104,44 +79,9 @@ print_normal (dis_info, value, attrs, pc, length) int length; { disassemble_info *info = dis_info; - - /* Print the operand as directed by the attributes. */ - if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_FAKE)) - ; /* nothing to do (??? at least not yet) */ - else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_PCREL_ADDR)) - (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info); - /* ??? Not all cases of this are currently caught. */ - else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_ABS_ADDR)) - /* FIXME: Why & 0xffffffff? */ - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "%ld", value); + (*info->fprintf_func) (info->stream, "#"); } -/* Keyword print handler. */ - -static void -print_keyword (dis_info, keyword_table, value, attrs) - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - CGEN_ATTR *attrs; -{ - disassemble_info *info = dis_info; - const CGEN_KEYWORD_ENTRY *ke; - - ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); -} - -/* -- disassembler routines inserted here */ -/* -- dis.c */ - #undef CGEN_PRINT_INSN #define CGEN_PRINT_INSN my_print_insn @@ -209,92 +149,95 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) switch (opindex) { case M32R_OPERAND_SR : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); break; case M32R_OPERAND_DR : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); break; case M32R_OPERAND_SRC1 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); break; case M32R_OPERAND_SRC2 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); break; case M32R_OPERAND_SCR : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r2); break; case M32R_OPERAND_DCR : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_r1); break; case M32R_OPERAND_SIMM8 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_simm8); break; case M32R_OPERAND_SIMM16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_simm16); break; case M32R_OPERAND_UIMM4 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm4); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm4); break; case M32R_OPERAND_UIMM5 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm5); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm5); break; case M32R_OPERAND_UIMM16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : { long value; - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_imm1 = ((value) + (1)); } break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCD : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_accd); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_accd); break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCS : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_accs); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_accs); break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACC : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_acc); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_acc); break; /* end-sanitize-m32rx */ + case M32R_OPERAND_HASH : + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil); + break; case M32R_OPERAND_HI16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_hi16); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_hi16); break; case M32R_OPERAND_SLO16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16); + length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16); break; case M32R_OPERAND_ULO16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm16); break; case M32R_OPERAND_UIMM24 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); break; case M32R_OPERAND_DISP8 : { long value; - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8 = ((value) << (2)); } break; case M32R_OPERAND_DISP16 : { long value; - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16 = ((value) << (2)); } break; case M32R_OPERAND_DISP24 : { long value; - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24 = ((value) << (2)); } break; @@ -352,23 +295,23 @@ m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length) print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<f_simm8, 0, pc, length); + print_normal (info, fields->f_simm8, 0|(1<f_simm16, 0, pc, length); + print_normal (info, fields->f_simm16, 0|(1<f_uimm4, 0|(1<f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_uimm16, 0|(1<f_imm1, 0|(1<f_imm1, 0|(1<f_acc, 0|(1<f_nil, 0, pc, length); + break; case M32R_OPERAND_HI16 : print_normal (info, fields->f_hi16, 0|(1<f_uimm16, 0|(1<f_uimm24, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<> (CGEN_BASE_INSN_BITSIZE - (start + length))) + & ((1 << length) - 1)); +#else + value = ((insn_value >> (total_length - (start + length))) + & ((1 << length) - 1)); +#endif + if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) + && (value & (1 << (length - 1)))) + value -= 1 << length; +#else + /* FIXME: unfinished */ +#endif + + *valuep = value; + + /* FIXME: for now */ + return 1; +} + +/* Default print handler. */ + +static void +print_normal (dis_info, value, attrs, pc, length) + PTR dis_info; + long value; + unsigned int attrs; + unsigned long pc; /* FIXME: should be bfd_vma */ + int length; +{ + disassemble_info *info = dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_FAKE)) + ; /* nothing to do (??? at least not yet) */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (pc + CGEN_PCREL_OFFSET + value, info); + /* ??? Not all cases of this are currently caught. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + /* FIXME: Why & 0xffffffff? */ + (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "%ld", value); +} + +/* Keyword print handler. */ + +static void +print_keyword (dis_info, keyword_table, value, attrs) + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs; +{ + disassemble_info *info = dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} /* Default insn extractor. diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index a48e73c8182..a7b13a61606 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -30,10 +30,13 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "m32r-opc.h" /* Look up instruction INSN_VALUE and extract its fields. - If non-null INSN is the insn table entry. + INSN, if non-null, is the insn table entry. Otherwise INSN_VALUE is examined to compute it. LENGTH is the bit length of INSN_VALUE if known, otherwise 0. + 0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'. + If INSN != NULL, LENGTH must be valid. ALIAS_P is non-zero if alias insns are to be included in the search. + The result a pointer to the insn table entry, or NULL if the instruction wasn't recognized. */ @@ -43,6 +46,7 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) cgen_insn_t insn_value; int length; CGEN_FIELDS *fields; + int alias_p; { char buf[16]; @@ -91,9 +95,15 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) extract handler. */ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn)) { - length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); - if (length > 0) - return insn; + int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, + insn_value, fields); + if (elength > 0) + { + /* sanity check */ + if (length != 0 && length != elength) + abort (); + return insn; + } } } @@ -106,43 +116,34 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) if (! alias_p && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) abort (); + /* Sanity check: length must be correct. */ + if (length != CGEN_INSN_BITSIZE (insn)) + abort (); length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); - if (length > 0) - return insn; + /* Sanity check: must succeed. + Could relax this later if it ever proves useful. */ + if (length == 0) + abort (); + return insn; } return NULL; } -/* Fill in the operand instances used by insn INSN_VALUE. - If non-null INS is the insn table entry. - Otherwise INSN_VALUE is examined to compute it. - LENGTH is the number of bits in INSN_VALUE if known, otherwise 0. +/* Fill in the operand instances used by INSN whose operands are FIELDS. INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. - The result a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ + in. */ -const CGEN_INSN * -m32r_cgen_get_insn_operands (insn, insn_value, length, indices) - const CGEN_INSN *insn; - cgen_insn_t insn_value; - int length; +void +m32r_cgen_get_insn_operands (insn, fields, indices) + const CGEN_INSN * insn; + const CGEN_FIELDS * fields; int *indices; { - CGEN_FIELDS fields; const CGEN_OPERAND_INSTANCE *opinst; int i; - /* FIXME: ALIAS insns are in transition from being record in the insn table - to being recorded separately as macros. They don't have semantic code - so they can't be used here. Thus we currently always ignore the INSN - argument. */ - insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0); - if (! insn) - return NULL; - for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); opinst != NULL && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; @@ -152,9 +153,35 @@ m32r_cgen_get_insn_operands (insn, insn_value, length, indices) if (op == NULL) indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); else - indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields); + indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), fields); } +} + +/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS + isn't known. + The INSN, INSN_VALUE, and LENGTH arguments are passed to + m32r_cgen_lookup_insn unchanged. + + The result is the insn table entry or NULL if the instruction wasn't + recognized. */ + +const CGEN_INSN * +m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices) + const CGEN_INSN *insn; + cgen_insn_t insn_value; + int length; + int *indices; +{ + CGEN_FIELDS fields; + + /* Pass non-zero for ALIAS_P only if INSN != NULL. + If INSN == NULL, we want a real insn. */ + insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields, + insn != NULL); + if (! insn) + return NULL; + m32r_cgen_get_insn_operands (insn, &fields, indices); return insn; } /* Attributes. */ @@ -204,6 +231,7 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { "ALIAS", NULL }, { "COND-CTI", NULL }, { "FILL-SLOT", NULL }, + { "NO-DIS", NULL }, { "PARALLEL", NULL }, { "RELAX", NULL }, { "RELAXABLE", NULL }, @@ -420,42 +448,42 @@ const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = #define INPUT CGEN_OPERAND_INSTANCE_INPUT #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT -static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = { { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, @@ -463,7 +491,7 @@ static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = { { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, @@ -471,7 +499,7 @@ static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, @@ -480,21 +508,21 @@ static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -502,14 +530,14 @@ static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 }, { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -517,7 +545,7 @@ static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 }, { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -526,7 +554,7 @@ static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 }, { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -537,7 +565,7 @@ static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 }, { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -547,48 +575,41 @@ static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = { { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = { { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = { - { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, - { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 }, - { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, - { 0 } -}; - /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { 0 } }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, @@ -596,7 +617,7 @@ static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -604,7 +625,7 @@ static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = { { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, @@ -612,20 +633,20 @@ static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, @@ -633,14 +654,14 @@ static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 }, { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, @@ -648,14 +669,14 @@ static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 }, { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, @@ -663,7 +684,7 @@ static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, @@ -671,25 +692,25 @@ static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = { { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = { { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = { { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = { { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, @@ -697,7 +718,7 @@ static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -706,7 +727,7 @@ static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -715,7 +736,7 @@ static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, @@ -723,7 +744,7 @@ static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 }, @@ -731,33 +752,33 @@ static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = { { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, @@ -765,7 +786,7 @@ static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 }, @@ -773,20 +794,20 @@ static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 }, { 0 } }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 }, { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 }, @@ -794,7 +815,7 @@ static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = { }; /* end-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = { { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 }, { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 }, { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 }, @@ -806,34 +827,34 @@ static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = { { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = { { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = { { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -841,14 +862,14 @@ static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = { { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -856,14 +877,14 @@ static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 }, { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = { { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -871,7 +892,7 @@ static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 }, @@ -879,7 +900,7 @@ static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = { { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 }, { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 }, { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 }, @@ -889,7 +910,7 @@ static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = { { 0 } }; -static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = { { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -899,7 +920,7 @@ static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = { }; /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, { 0 } @@ -907,7 +928,7 @@ static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 }, { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 }, @@ -916,7 +937,7 @@ static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 }, { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 }, { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 }, @@ -925,7 +946,7 @@ static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = { { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, @@ -935,7 +956,7 @@ static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = { { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 }, { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 }, { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 }, @@ -944,7 +965,7 @@ static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = { +static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = { { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 }, { 0 } }; @@ -957,468 +978,356 @@ static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = { #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) -/* The instruction table. */ +/* The instruction table. + This is currently non-static because the simulator accesses it + directly. */ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { - /* null first entry, end of all hash chains */ + /* Special null first entry. + A `num' value of zero is thus illegal. + Also, the special `illegal' insn resides here. */ { { 0 }, 0 }, /* add $dr,$sr */ { { 1, 1, 1, 1 }, - "add", "add", + M32R_INSN_ADD, "add", "add", { MNEM, ' ', OP (DR), ',', OP (SR), 0 }, { 16, 16, 0xf0f0 }, 0xa0, - & fmt_0_add_ops[0], + (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<