From: Clifford Wolf Date: Thu, 1 Jun 2017 10:43:21 +0000 (+0200) Subject: Fix handling of Verilog ~& and ~| operators X-Git-Tag: yosys-0.8~419 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=129984e115d318e00ec065ea76cb8c5926393bc4;p=yosys.git Fix handling of Verilog ~& and ~| operators --- diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 26201d618..154b59ebc 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1537,10 +1537,18 @@ basic_expr: $$ = new AstNode(AST_BIT_AND, $1, $4); append_attr($$, $3); } | + basic_expr OP_NAND attr basic_expr { + $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4)); + append_attr($$, $3); + } | basic_expr '|' attr basic_expr { $$ = new AstNode(AST_BIT_OR, $1, $4); append_attr($$, $3); } | + basic_expr OP_NOR attr basic_expr { + $$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4)); + append_attr($$, $3); + } | basic_expr '^' attr basic_expr { $$ = new AstNode(AST_BIT_XOR, $1, $4); append_attr($$, $3);