From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 7 Sep 2018 09:51:17 +0000 (+0200)
Subject: soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some... 
X-Git-Tag: 24jan2021_ls180~1620
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12a89447111076913ce98ed08b52375211188fb3;p=litex.git

soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...)
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 53943269..238ede4c 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -72,8 +72,15 @@ class SoCSDRAM(SoCCore):
 
         if self.l2_size:
             port = self.sdram.crossbar.get_port()
-            self.submodules.l2_cache = wishbone.Cache(
-                self.l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
+            l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.dw))
+            # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
+            # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
+            from litex.build.xilinx.vivado import XilinxVivadoToolchain
+            if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
+                from migen.fhdl.simplify import FullMemoryWE
+                self.submodules.l2_cache = FullMemoryWE()(l2_cache)
+            else:
+                self.submodules.l2_cache = l2_cache
             self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
 
     def do_finalize(self):