From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 7 Sep 2020 16:18:25 +0000 (+0100)
Subject: convert shift_rot to subset decoder
X-Git-Tag: semi_working_ecp5~142
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12b2bd2034c535e6828f9ba6842e7af5a8e4d24e;p=soc.git

convert shift_rot to subset decoder
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 34d4736e..f94fecea 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -290,9 +290,11 @@ class TestRunner(unittest.TestCase):
         comb = m.d.comb
         instruction = Signal(32)
 
-        pdecode = create_pdecode()
+        fn_name = "SHIFT_ROT"
+        opkls = ShiftRotPipeSpec.opsubsetkls
 
-        m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+        m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
+        pdecode = pdecode2.dec
 
         pspec = ShiftRotPipeSpec(id_wid=2)
         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
@@ -321,7 +323,7 @@ class TestRunner(unittest.TestCase):
 
     def check_alu_outputs(self, alu, dec2, sim, code):
 
-        rc = yield dec2.e.do.rc.data
+        rc = yield dec2.e.do.rc.rc
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data