From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 9 May 2020 17:06:48 +0000 (-0400)
Subject: Implement logical shift right
X-Git-Tag: div_pipeline~1306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12b786daa88080d85e6f981bdee0f15a1561b0be;p=soc.git

Implement logical shift right
---

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index ab89c2db..e66a769e 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -38,12 +38,13 @@ class ALUMainStage(PipeModBase):
         m.submodules.maskgen = maskgen = MaskGen(64)
         m.submodules.rotl = rotl = ROTL(64)
         m.submodules.rotl32 = rotl32 = ROTL(32)
+        rotate_amt = Signal.like(rotl.b)
 
         comb += [
             rotl.a.eq(self.i.a),
-            rotl.b.eq(self.i.b),
+            rotl.b.eq(rotate_amt),
             rotl32.a.eq(self.i.a[0:32]),
-            rotl32.b.eq(self.i.b)]
+            rotl32.b.eq(rotate_amt)]
 
         with m.If(is_32bit):
             comb += rotl_out.eq(Cat(rotl32.o, Repl(0, 32)))
@@ -65,6 +66,22 @@ class ALUMainStage(PipeModBase):
             with m.Case(InternalOp.OP_SHL):
                 comb += maskgen.mb.eq(Mux(is_32bit, 32, 0))
                 comb += maskgen.me.eq(63-self.i.b[0:6])
+                comb += rotate_amt.eq(self.i.b[0:6])
+                with m.If(is_32bit):
+                    with m.If(self.i.b[5]):
+                        comb += mask.eq(0)
+                    with m.Else():
+                        comb += mask.eq(maskgen.o)
+                with m.Else():
+                    with m.If(self.i.b[6]):
+                        comb += mask.eq(0)
+                    with m.Else():
+                        comb += mask.eq(maskgen.o)
+                comb += self.o.o.eq(rotl_out & mask)
+            with m.Case(InternalOp.OP_SHR):
+                comb += maskgen.mb.eq(Mux(is_32bit, 32, 0) + self.i.b[0:6])
+                comb += maskgen.me.eq(63)
+                comb += rotate_amt.eq(64-self.i.b[0:6])
                 with m.If(is_32bit):
                     with m.If(self.i.b[5]):
                         comb += mask.eq(0)
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 85ae6206..3be8d3ef 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -125,8 +125,8 @@ class ALUTestCase(FHDLTestCase):
                 sim = self.run_tst_program(program, initial_regs)
 
     def test_shift(self):
-        insns = ["slw", "sld"]
-        for i in range(10):
+        insns = ["slw", "sld", "srw", "srd"]
+        for i in range(20):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
             initial_regs = [0] * 32