From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 5 Apr 2020 19:11:49 +0000 (-0400)
Subject: Add in _reg and immediate support
X-Git-Tag: div_pipeline~1468
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12da93b9b088ab6cf9ee83b1fd46c5bc3035c32a;p=soc.git

Add in _reg and immediate support
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index bd946988..835c9b48 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -124,8 +124,10 @@ class ISACaller:
         self.mem.memassign(ea, sz, val)
 
     def prep_namespace(self):
-        si = yield self.decoder.SI
-        self.namespace['SI'] = SelectableInt(si, bits=16)
+        for name in ['SI', 'UI', 'D', 'BD']:
+            signal = getattr(self.decoder, name)
+            val = yield signal
+            self.namespace[name] = SelectableInt(val, bits=signal.width)
 
     def call(self, name):
         yield from self.prep_namespace()
@@ -137,17 +139,22 @@ class ISACaller:
         inputs = []
         for name in input_names:
             regnum = yield getattr(self.decoder, name)
+            regname = "_" + name
+            self.namespace[regname] = regnum
             print('reading reg %d' % regnum)
             inputs.append(self.gpr(regnum))
         print(inputs)
         results = function(self, *inputs)
         print(results)
 
-        output_names = create_args(write_regs)
-        for name, output in zip(output_names, results):
-            regnum = yield getattr(self.decoder, name)
-            print('writing reg %d' % regnum)
-            self.gpr[regnum] = output.narrow(64)
+        if write_regs:
+            output_names = create_args(write_regs)
+            for name, output in zip(output_names, results):
+                regnum = yield getattr(self.decoder, name)
+                print('writing reg %d' % regnum)
+                if isinstance(output, int):
+                    output = SelectableInt(output, 64)
+                self.gpr[regnum] = output
 
 
 def inject():
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index aa6f23ae..d0a97df6 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -69,6 +69,16 @@ class DecoderTestCase(FHDLTestCase):
             print(sim.gpr(1))
             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
 
+    def test_load_store(self):
+        lst = ["addi 1, 0, 0x0010",
+               "addi 2, 0, 0x1234",
+               "stw 2, 0(1)",
+               "lwz 3, 0(1)"]
+        with Program(lst) as program:
+            sim = self.run_test_program(program)
+            print(sim.gpr(1))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+
     def run_test_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)
         simulator.gpr.dump()