From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Jun 2021 20:12:48 +0000 (+0100)
Subject: add sv bitrev "major" CSV table
X-Git-Tag: xlen-bcd~404
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12eaf7b45e6512e706d8ac07368600c9aeff045a;p=openpower-isa.git

add sv bitrev "major" CSV table
---

diff --git a/openpower/isatables/svldstmajor.csv b/openpower/isatables/svldstmajor.csv
new file mode 100644
index 00000000..1c300126
--- /dev/null
+++ b/openpower/isatables/svldstmajor.csv
@@ -0,0 +1,23 @@
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,SVD
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,SVD
+50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,SVD
+51,LDST,OP_LOAD,RA,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,SVD
+48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,SVD
+49,LDST,OP_LOAD,RA,CONST_SSI,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,SVD
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,SVD
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,SVD
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,SVD
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,SVD
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,SVD
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SSI,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,SVD
+38,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,SVD
+39,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,SVD
+54,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stfd,SVD
+55,LDST,OP_STORE,RA,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stfdu,SVD
+52,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,stfs,SVD
+53,LDST,OP_STORE,RA,CONST_SSI,FRS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,stfsu,SVD
+44,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,SVD
+45,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,SVD
+36,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,SVD
+37,LDST,OP_STORE,RA_OR_ZERO,CONST_SSI,RS,RC,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu,SVD
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 0788642b..ad5b91c3 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -403,6 +403,7 @@ class In2Sel(Enum):
     SPR = 12
     RS = 13  # for shiftrot (M-Form)
     FRB = 14
+    CONST_SSI = 15 # for SVD-Form
 
 
 @unique