From: Anton Blanchard <anton@linux.ibm.com>
Date: Mon, 9 Aug 2021 03:49:25 +0000 (+1000)
Subject: liteeth: Update yaml config
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=12efb51bcc7024ba78175ad7cbfa23837ad2ac89;p=microwatt.git

liteeth: Update yaml config

csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/liteeth/gen-src/arty.yml b/liteeth/gen-src/arty.yml
index 7200a70..d092c0a 100644
--- a/liteeth/gen-src/arty.yml
+++ b/liteeth/gen-src/arty.yml
@@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   100e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2
 
 soc:
     mem_map:
         ethmac: 0x00010000
-    csr_data_width: 32
diff --git a/liteeth/gen-src/nexys-video.yml b/liteeth/gen-src/nexys-video.yml
index 38a207c..d7253ea 100644
--- a/liteeth/gen-src/nexys-video.yml
+++ b/liteeth/gen-src/nexys-video.yml
@@ -8,8 +8,9 @@ vendor:     xilinx
 clk_freq:   125e6
 core:       wishbone
 endianness: little
+ntxslots:   2
+nrxslots:   2
 
 soc:
     mem_map:
         ethmac: 0x00010000
-    csr_data_width: 32