From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 21:21:59 +0000 (-0800)
Subject: Fix multiple driver issue
X-Git-Tag: working-ls180~778^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=130d3b9639148fa8191937313a3ad21a7827df18;p=yosys.git

Fix multiple driver issue
---

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index b21b0de01..839f8561c 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -228,11 +228,16 @@ struct SubmodWorker
 				RTLIL::SigSpec old_sig = sigmap(it.first);
 				RTLIL::Wire *new_wire = it.second.new_wire;
 				if (new_wire->port_id > 0) {
-					// Prevents "ERROR: Mismatch in directionality ..." when flattening
 					if (new_wire->port_output)
-						for (auto &b : old_sig)
+						for (int i = 0; i < GetSize(old_sig); i++) {
+							auto &b = old_sig[i];
+							// Prevents "ERROR: Mismatch in directionality ..." when flattening
 							if (!b.wire)
 								b = module->addWire(NEW_ID);
+							// Prevents "Warning: multiple conflicting drivers ..."
+							else if (!it.second.is_int_driven[i])
+								b = module->addWire(NEW_ID);
+						}
 					new_cell->setPort(new_wire->name, old_sig);
 				}
 			}