From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 May 2021 12:27:53 +0000 (+0100)
Subject: add first pypowersim example
X-Git-Tag: xlen-bcd~580
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=131570fb8e04b63f7d9c4a7c8869d9dbc87794d3;p=openpower-isa.git

add first pypowersim example
---

diff --git a/src/test/basic_pypowersim/Makefile b/src/test/basic_pypowersim/Makefile
new file mode 100644
index 00000000..f3ddf216
--- /dev/null
+++ b/src/test/basic_pypowersim/Makefile
@@ -0,0 +1,21 @@
+TOOLCHAIN=powerpc64-linux-gnu
+CC=$(TOOLCHAIN)-gcc
+AS=$(TOOLCHAIN)-as
+AFLAGS=-mpwr9
+
+all: sim
+
+sim: kernel.bin
+	pypowersim -i kernel.bin
+
+clean:
+	rm *.o *.elf *.bin
+
+kernel.elf: test.o
+	$(TOOLCHAIN)-ld $^ -EL -o $@ -T memmap
+
+kernel.bin: kernel.elf
+	$(TOOLCHAIN)-objcopy $< -I elf64-little -O binary $@
+
+%.o: %.s
+	$(AS) $(AFLAGS) -c $< -le -o $@
diff --git a/src/test/basic_pypowersim/memmap b/src/test/basic_pypowersim/memmap
new file mode 100644
index 00000000..8cc1a16e
--- /dev/null
+++ b/src/test/basic_pypowersim/memmap
@@ -0,0 +1,11 @@
+
+MEMORY
+{
+    ram  : ORIGIN = 0x20000000, LENGTH = 128M
+}
+
+SECTIONS
+{
+   .text : { *(.text*) } > ram
+   .bss  : { *(.text*) } > ram
+}
diff --git a/src/test/basic_pypowersim/test.s b/src/test/basic_pypowersim/test.s
new file mode 100644
index 00000000..fb2ec156
--- /dev/null
+++ b/src/test/basic_pypowersim/test.s
@@ -0,0 +1,6 @@
+	lis 1, 0xdead
+	ori 1, 1, 0xbeef
+	lis 2, 0x2000
+	ori 2, 2, 0x0100
+	std 1, 0(2)
+	lhz 1, 4(2)