From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 17:38:04 +0000 (+0000)
Subject: set power type in fake pll vdd/vss
X-Git-Tag: LS180_RC3~27^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=131b93797570728c4158cec388cd3354af104b64;p=soclayout.git

set power type in fake pll vdd/vss
---

diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py
index 03a6ccc..07a89a9 100644
--- a/experiments10_verilog/pll.py
+++ b/experiments10_verilog/pll.py
@@ -237,6 +237,8 @@ def _load():
         nets['div_out_test'].setDirection( Net.Direction.OUT )
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
+        nets['vdd'].setType( Net.Type.POWER )
+        nets['vss'].setType( Net.Type.GROUND )
 
         # create series of stepped pins
         x = space*20
diff --git a/experiments9/pll.py b/experiments9/pll.py
index 03a6ccc..07a89a9 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -237,6 +237,8 @@ def _load():
         nets['div_out_test'].setDirection( Net.Direction.OUT )
         nets['vco_test_ana'].setDirection( Net.Direction.OUT )
         nets['out_v'].setDirection( Net.Direction.OUT )
+        nets['vdd'].setType( Net.Type.POWER )
+        nets['vss'].setType( Net.Type.GROUND )
 
         # create series of stepped pins
         x = space*20