From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 4 Nov 2013 07:28:13 +0000 (+0100)
Subject: Fixes for early width and sign detection in ast simplifier
X-Git-Tag: yosys-0.2.0~415
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1325514d33e553ab41314e5bc2f879bfd38511c7;p=yosys.git

Fixes for early width and sign detection in ast simplifier
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e6db61604..e5cc7c4cc 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -242,7 +242,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		width_hint = -1;
 		sign_hint = true;
 		for (auto child : children) {
-			while (child->simplify(false, false, false, stage, -1, false) == true) { }
+			while (child->simplify(false, false, in_lvalue, stage, -1, false) == true) { }
 			child->detectSignWidthWorker(width_hint, sign_hint);
 		}
 		reset_width_after_children = true;
@@ -851,6 +851,7 @@ skip_dynamic_range_lvalue_expansion:;
 			wire->is_output = false;
 
 			current_ast_mod->children.push_back(wire);
+			while (wire->simplify(true, false, false, 1, -1, false)) { }
 
 			AstNode *lvalue = new AstNode(AST_IDENTIFIER);
 			lvalue->str = wire->str;