From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 May 2021 10:28:38 +0000 (+0100)
Subject: add setting of qemu GPRs/FPRs in pypowersim
X-Git-Tag: xlen-bcd~535
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=132d38b3e273919b5cb963194a7233035b7e0897;p=openpower-isa.git

add setting of qemu GPRs/FPRs in pypowersim
---

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 6f561309..9bdec27b 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -132,6 +132,13 @@ def run_tst(args, generator, qemu,
         qemu = run_program(generator, initial_mem=mem, 
                 bigendian=False, start_addr=initial_pc,
                 continuous_run=False)
+        # TODO: SPRs.  how??
+        if initial_regs is not None:
+            for reg, val in enumerate(initial_regs):
+                qemu.set_gpr(reg, val)
+        if initial_fprs is not None:
+            for fpr, val in enumerate(initial_fprs):
+                qemu.set_fpr(fpr, val)
 
     m = Module()
     comb = m.d.comb
diff --git a/src/openpower/simulator/qemu.py b/src/openpower/simulator/qemu.py
index 830851e3..cdbee4f6 100644
--- a/src/openpower/simulator/qemu.py
+++ b/src/openpower/simulator/qemu.py
@@ -125,11 +125,11 @@ class QemuController:
 
     def set_gpr(self, reg, val):
         self._rcache_trash('x %d' % reg)
-        self.gdb_eval('$r%d=%d' % (reg, pc))
+        self.gdb_eval('$r%d=%d' % (reg, val))
 
     def set_fpr(self, reg, val):
         self._rcache_trash('x %d' % (reg+32))
-        self.gdb_eval('$fp%d=%d' % (reg, pc))
+        self.gdb_eval('$fp%d=%d' % (reg, val))
 
     def set_pc(self, pc):
         self._rcache_trash('x 64')