From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 14:07:49 +0000 (+0100)
Subject: remove (invalid) NormalSaturationExtRM mode from power_insn.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=132f5e594b7e053f7428f64099b9072438269d47;p=openpower-isa.git

remove (invalid) NormalSaturationExtRM mode from power_insn.py
(was in SUBVL>1 which is now gone)
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index f1744728..8a7ef5b8 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1389,24 +1389,6 @@ class NormalSaturationRM(NormalBaseRM):
         yield from super().specifiers
 
 
-class NormalSaturationExtRM(NormalBaseRM):
-    """normal: sat mode: N=0/1 u/s, SUBVL>1"""
-    N: BaseRM.mode[2]
-    zz: BaseRM.mode[3]
-    dz: BaseRM.mode[3]
-    sz: BaseRM.mode[3]
-
-    @property
-    def specifiers(self):
-        if self.zz:
-            yield f"zz"
-        if self.N:
-            yield "sats"
-        else:
-            yield "satu"
-        yield from super().specifiers
-
-
 class NormalPredResultRc1RM(NormalBaseRM):
     """normal: Rc=1: pred-result CR sel"""
     inv: BaseRM.mode[2]
@@ -1435,7 +1417,6 @@ class NormalRM(NormalBaseRM):
     ffrc1: NormalFailFirstRc1RM
     ffrc0: NormalFailFirstRc0RM
     sat: NormalSaturationRM
-    satx: NormalSaturationExtRM
     prrc1: NormalPredResultRc1RM
     prrc0: NormalPredResultRc0RM