From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 18:22:20 +0000 (+0100)
Subject: Fixed parsing of verilog macros at end of line
X-Git-Tag: yosys-0.2.0~158
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13359d65ba8cc4a968b5b27deef4040fb2430899;p=yosys.git

Fixed parsing of verilog macros at end of line
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 5cfa0f24b..db53e8c68 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -386,7 +386,7 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
 			std::string name = tok.substr(1);
 			// printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str());
 			std::string skipped_spaces = skip_spaces();
-			tok = next_token(true);
+			tok = next_token(false);
 			if (tok == "(" && defines_with_args.count(name) > 0) {
 				int level = 1;
 				std::vector<std::string> args;