From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 28 Apr 2016 06:07:21 +0000 (-0700)
Subject: Added GP_PGA cell
X-Git-Tag: yosys-0.7~236^2^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=134e093e4e86080e1e4066f32128d268a36aeee5;p=yosys.git

Added GP_PGA cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1152ffe63..b7dbe81a2 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -153,6 +153,17 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
 	
 endmodule
 
+module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
+
+	parameter GAIN = 1;
+	parameter INPUT_MODE = "SINGLE";
+
+	initial VOUT = 0;
+
+	//cannot simulate mixed signal IP
+
+endmodule
+
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;