From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 11 Dec 2013 21:26:10 +0000 (+0100)
Subject: fhdl/verilog: fix representation of negative integers
X-Git-Tag: 24jan2021_ls180~2099^2~393
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=135a4fea25a776fcce0c8f19a23df26fcb34140c;p=litex.git

fhdl/verilog: fix representation of negative integers

Give the explicit two's complement representation for the given bit width.

This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index fc56f784..684812a5 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -27,7 +27,8 @@ def _printintbool(node):
 		if node >= 0:
 			return str(bits_for(node)) + "'d" + str(node), False
 		else:
-			return "-" + str(bits_for(node)) + "'sd" + str(-node), True
+			nbits = bits_for(node)
+			return str(nbits) + "'sd" + str(2**nbits + node), True
 	else:
 		raise TypeError