From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 21 Feb 2017 02:48:35 +0000 (-0800)
Subject: serialize simulator on wfi
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13639b9c457b3879efa620ce55abddbdc834ce68;p=riscv-isa-sim.git

serialize simulator on wfi

This improves simulator perf when a thread is idle, or waiting on HTIF.
---

diff --git a/riscv/decode.h b/riscv/decode.h
index b607bf3..d82767d 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -202,9 +202,10 @@ private:
      } while(0)
 
 #define set_pc_and_serialize(x) \
-  do { set_pc(x); /* check alignment */ \
+  do { reg_t __npc = (x); \
+       set_pc(__npc); /* check alignment */ \
        npc = PC_SERIALIZE_AFTER; \
-       STATE.pc = (x); \
+       STATE.pc = __npc; \
      } while(0)
 
 /* Sentinel PC values to serialize simulator pipeline */
diff --git a/riscv/execute.cc b/riscv/execute.cc
index ebc9dc7..1b53ccf 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -84,7 +84,7 @@ void processor_t::step(size_t n)
      if (unlikely(invalid_pc(pc))) { \
        switch (pc) { \
          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
-         case PC_SERIALIZE_AFTER: instret++; break; \
+         case PC_SERIALIZE_AFTER: n = ++instret; break; \
          default: abort(); \
        } \
        pc = state.pc; \
diff --git a/riscv/insns/wfi.h b/riscv/insns/wfi.h
index 6f037f8..643c374 100644
--- a/riscv/insns/wfi.h
+++ b/riscv/insns/wfi.h
@@ -1 +1 @@
-// nop
+set_pc_and_serialize(npc);