From: Kyrylo Tkachov Date: Tue, 29 Oct 2013 12:22:35 +0000 (+0000) Subject: arm.c (cortexa7_extra_costs): New table. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1375873827fca8f264c4c429254702631c20aa63;p=gcc.git arm.c (cortexa7_extra_costs): New table. 2013-10-29 Kyrylo Tkachov * config/arm/arm.c (cortexa7_extra_costs): New table. (arm_cortex_a7_tune): New. * config/arm/arm-cores.def: Use cortex_a7 tuning for cortex-a7. From-SVN: r204157 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d749ff46438..5855f116b1e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-10-29 Kyrylo Tkachov + + * config/arm/arm.c (cortexa7_extra_costs): New table. + (arm_cortex_a7_tune): New. + * config/arm/arm-cores.def: Use cortex_a7 tuning for cortex-a7. + 2013-10-29 Eric Botcazou * expr.c (expand_expr_real_1) : Eliminate small redundancy. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 17c9bf3255a..79e2e87b72b 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -125,7 +125,7 @@ ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2) ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2) ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) -ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex) +ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 78554e8be2f..212a4bcc7dc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1152,6 +1152,107 @@ const struct cpu_cost_table cortexa9_extra_costs = }; +const struct cpu_cost_table cortexa7_extra_costs = +{ + /* ALU */ + { + 0, /* Arith. */ + 0, /* Logical. */ + COSTS_N_INSNS (1), /* Shift. */ + COSTS_N_INSNS (1), /* Shift_reg. */ + COSTS_N_INSNS (1), /* Arith_shift. */ + COSTS_N_INSNS (1), /* Arith_shift_reg. */ + COSTS_N_INSNS (1), /* Log_shift. */ + COSTS_N_INSNS (1), /* Log_shift_reg. */ + COSTS_N_INSNS (1), /* Extend. */ + COSTS_N_INSNS (1), /* Extend_arith. */ + COSTS_N_INSNS (1), /* Bfi. */ + COSTS_N_INSNS (1), /* Bfx. */ + COSTS_N_INSNS (1), /* Clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + + { + /* MULT SImode */ + { + 0, /* Simple. */ + COSTS_N_INSNS (1), /* Flag_setting. */ + COSTS_N_INSNS (1), /* Extend. */ + COSTS_N_INSNS (1), /* Add. */ + COSTS_N_INSNS (1), /* Extend_add. */ + COSTS_N_INSNS (7) /* Idiv. */ + }, + /* MULT DImode */ + { + 0, /* Simple (N/A). */ + 0, /* Flag_setting (N/A). */ + COSTS_N_INSNS (1), /* Extend. */ + 0, /* Add. */ + COSTS_N_INSNS (2), /* Extend_add. */ + 0 /* Idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (1), /* Load. */ + COSTS_N_INSNS (1), /* Load_sign_extend. */ + COSTS_N_INSNS (3), /* Ldrd. */ + COSTS_N_INSNS (1), /* Ldm_1st. */ + 1, /* Ldm_regs_per_insn_1st. */ + 2, /* Ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* Loadf. */ + COSTS_N_INSNS (2), /* Loadd. */ + COSTS_N_INSNS (1), /* Load_unaligned. */ + COSTS_N_INSNS (1), /* Store. */ + COSTS_N_INSNS (3), /* Strd. */ + COSTS_N_INSNS (1), /* Stm_1st. */ + 1, /* Stm_regs_per_insn_1st. */ + 2, /* Stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* Storef. */ + COSTS_N_INSNS (2), /* Stored. */ + COSTS_N_INSNS (1) /* Store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (15), /* Div. */ + COSTS_N_INSNS (3), /* Mult. */ + COSTS_N_INSNS (7), /* Mult_addsub. */ + COSTS_N_INSNS (7), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (3), /* Fpconst. */ + COSTS_N_INSNS (3), /* Neg. */ + COSTS_N_INSNS (3), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (30), /* Div. */ + COSTS_N_INSNS (6), /* Mult. */ + COSTS_N_INSNS (10), /* Mult_addsub. */ + COSTS_N_INSNS (7), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (3), /* Fpconst. */ + COSTS_N_INSNS (3), /* Neg. */ + COSTS_N_INSNS (3), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* Alu. */ + } +}; + const struct cpu_cost_table cortexa15_extra_costs = { /* ALU */ @@ -1368,6 +1469,22 @@ const struct tune_params arm_cortex_tune = false /* Prefer Neon for 64-bits bitops. */ }; +const struct tune_params arm_cortex_a7_tune = +{ + arm_9e_rtx_costs, + &cortexa7_extra_costs, + NULL, + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ +}; + const struct tune_params arm_cortex_a15_tune = { arm_9e_rtx_costs,