From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 23:16:13 +0000 (-0800)
Subject: Use "write_edif -pvector bra" for Xilinx EDIF files
X-Git-Tag: yosys-0.9~271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13844c765818b5d8c0d16d62dcc530f688d2c28a;p=yosys.git

Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c11d885d..3632f348f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -252,7 +252,7 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "edif"))
 		{
 			if (!edif_file.empty())
-				Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
+				Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
 		}
 		if (check_label(active, run_from, run_to, "blif"))
 		{