From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 07:25:40 +0000 (+0200)
Subject: Update CHANGELOG
X-Git-Tag: yosys-0.8~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=138ba7126414a3d524e7edfbbce2bdf590ac8a21;p=yosys.git

Update CHANGELOG

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/CHANGELOG b/CHANGELOG
index c1e93c37d..5499c309a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,11 +3,13 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???    (2017-12-12)
+Yosys 0.7 .. Yosys 0.8
 ----------------------
 
  * Various
     - Many bugfixes and small improvements
+    - Strip debug symbols from installed binary
+    - Replace -ignore_redef with -[no]overwrite in front-ends
     - Added write_verilog hex dump support, add -nohex option
     - Added "write_verilog -decimal"
     - Added "scc -set_attr"
@@ -17,7 +19,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added FIRRTL back-end
     - Improved ABC default scripts
     - Added "design -reset-vlog"
-    - Added "yosys -W regex" and "yosys -w regex"
+    - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
@@ -42,10 +44,25 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "ltp" command
     - Added support for editline as replacement for readline
     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
+    - Added "yosys -E" for creating Makefile dependencies files
+    - Added "synth -noshare"
+    - Added "memory_nordff"
+    - Added "setundef -undef -expose -anyconst"
+    - Added "expose -input"
+    - Added specify/specparam parser support (simply ignore them)
+    - Added "write_blif -inames -iattr"
+    - Added "hierarchy -simcheck"
+    - Added an option to statically link abc into yosys
+    - Added protobuf back-end
+    - Added BLIF parsing support for .conn and .cname
+    - Added read_verilog error checking for reg/wire/logic misuse
+    - Added "make coverage" and ENABLE_GCOV build option
 
  * Changes in Yosys APIs
     - Added ConstEval defaultval feature
     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
+    - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
+    - Added log_file_warning() and log_file_error() functions
 
  * Formal Verification
     - Added "write_aiger"
@@ -61,6 +78,13 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
     - Added a brand new "write_btor" command for BTOR2
+    - Added clk2fflogic memory support and other improvements
+    - Added "async memory write" support to write_smt2
+    - Simulate clock toggling in yosys-smtbmc VCD output
+    - Added $allseq/$allconst cells for EA-solving
+    - Make -nordff the default in "prep"
+    - Added (* gclk *) attribute
+    - Added "async2sync" pass for single-clock designs with async resets
 
  * Verific support
     - Many improvements in Verific front-end
@@ -69,16 +93,24 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "verific -import -flatten" and "verific -import -extnets"
     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
     - Remove PSL support (because PSL has been removed in upstream Verific)
+    - Improve integration with "hierarchy" command design elaboration
+    - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
+    - Added simpilied "read" command that automatically uses verific if available
+    - Added "verific -set-<severity> <msg_id>.."
+    - Added "verific -work <libname>"
 
  * New back-ends
     - Added initial Coolrunner-II support
     - Added initial eASIC support
+    - Added initial ECP5 support
 
  * GreenPAK Support
     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 
  * iCE40 Support
     - Add "synth_ice40 -vpr"
+    - Add "synth_ice40 -nodffe"
+    - Add "synth_ice40 -json"
     - Add Support for UltraPlus cells
 
  * MAX10 and Cyclone IV Support
@@ -89,6 +121,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added example of implementation for DE2i-150 board.
     - Added example of implementation for MAX10 development kit.
     - Added LFSR example from Asic World.
+    - Added "dffinit -highlow" for mapping to Intel primitives
 
 
 Yosys 0.6 .. Yosys 0.7