From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 18 Nov 2019 13:50:02 +0000 (+0000)
Subject: arch-arm: Fix NumVecV7ArchRegs value (64->16)
X-Git-Tag: v19.0.0.0~214
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1398a81618e18405afaeb31197929df2dd1cf5f4;p=gem5.git

arch-arm: Fix NumVecV7ArchRegs value (64->16)

In armv7 there are 16 only quadword (vector) registers which are usable
by SIMD instructions (Q0-Q15). Those completely overlap with the 32
double word registers (D0-D31).

NumVecV7ArchRegs  = 16; // Q0-Q15

Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 7f6309bea..f2dfce425 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -88,8 +88,8 @@ const int NumMiscRegs = NUM_MISCREGS;
 
 // Vec, PredVec
 const int NumFloatV7ArchRegs  = 64;
-const int NumVecV7ArchRegs  = 64;
-const int NumVecV8ArchRegs  = 32;
+const int NumVecV7ArchRegs  = 16; // Q0-Q15
+const int NumVecV8ArchRegs  = 32; // V0-V31
 const int NumVecSpecialRegs = 8;
 const int NumVecIntrlvRegs = 4;
 const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;