From: lkcl Date: Wed, 30 Dec 2020 15:38:42 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~723 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13a4e7ee88b301c8a025b218bf9cb6325b94cfca;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 2408836a0..1e293462e 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -455,8 +455,10 @@ which is normally only what VCOMPRESS and VEXPAND do in traditional Vector ISAs: move registers. Twin Predication can be applied to `extsw` or `fcvt`, LD/ST operations and even `rlwinmi` and other operations taking a single source and immediate(s) such as `addi`. All of these -are termed single-source, single-destination (LDST Address-generation, -or AGEN, is a single source). +are termed single-source, single-destination. + +LDST Address-generation, +or AGEN, is a special case of single source, because elwidth overriding does not make sense to apply to the computation of the 64 bit address itself, but it *does* make sense to apply elwidth overrides to the data being accessed *at* that address. It also turns out that by using a single bit set in the source or destination, *all* the sequential ordered standard patterns of Vector