From: Joel Stanley Date: Thu, 25 Aug 2022 09:51:07 +0000 (+1000) Subject: antmicro-artix-dc-scm: Add liteeth X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13aa52dfa742de446b4bc50d4d58ffd16ca89f84;p=microwatt.git antmicro-artix-dc-scm: Add liteeth As with the DRAM configuration, the DC-SCM board uses the same PHY as the Nexys Video and works with it's generated VHDL. Signed-off-by: Joel Stanley --- diff --git a/fpga/top-antmicro-artix-dc-scm.vhdl b/fpga/top-antmicro-artix-dc-scm.vhdl index ca17a96..b8fd75f 100644 --- a/fpga/top-antmicro-artix-dc-scm.vhdl +++ b/fpga/top-antmicro-artix-dc-scm.vhdl @@ -24,7 +24,7 @@ entity toplevel is SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_QUAD : boolean := true; LOG_LENGTH : natural := 512; - USE_LITEETH : boolean := false; + USE_LITEETH : boolean := true; UART_IS_16550 : boolean := false; HAS_UART1 : boolean := true; USE_LITESDCARD : boolean := false; @@ -51,6 +51,17 @@ entity toplevel is spi_flash_wp_n : inout std_ulogic; spi_flash_hold_n : inout std_ulogic; + -- Ethernet + eth_clocks_tx : out std_ulogic; + eth_clocks_rx : in std_ulogic; + eth_rst_n : out std_ulogic; + eth_int_n : in std_ulogic; + eth_mdio : inout std_ulogic; + eth_mdc : out std_ulogic; + eth_rx_ctl : in std_ulogic; + eth_rx_data : in std_ulogic_vector(3 downto 0); + eth_tx_ctl : out std_ulogic; + eth_tx_data : out std_ulogic_vector(3 downto 0); -- DRAM wires ddram_a : out std_ulogic_vector(14 downto 0); @@ -80,13 +91,14 @@ architecture behaviour of toplevel is -- Internal clock signals: signal system_clk : std_ulogic; signal system_clk_locked : std_ulogic; - signal eth_clk_locked : std_ulogic; -- External IOs from the SoC signal wb_ext_io_in : wb_io_master_out; signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_eth : std_ulogic; + -- DRAM main data wishbone connection signal wb_dram_in : wishbone_master_out; @@ -223,7 +235,7 @@ begin wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_init => wb_ext_is_dram_init, --- wb_ext_is_eth => , + wb_ext_is_eth => wb_ext_is_eth, -- wb_ext_is_sdcard => , -- DMA wishbone @@ -400,12 +412,91 @@ begin end generate; - wb_ext_io_out <= wb_dram_ctrl_out; + has_liteeth : if USE_LITEETH generate + + component liteeth_core port ( + sys_clock : in std_ulogic; + sys_reset : in std_ulogic; + rgmii_eth_clocks_tx : out std_ulogic; + rgmii_eth_clocks_rx : in std_ulogic; + rgmii_eth_rst_n : out std_ulogic; + rgmii_eth_int_n : in std_ulogic; + rgmii_eth_mdio : inout std_ulogic; + rgmii_eth_mdc : out std_ulogic; + rgmii_eth_rx_ctl : in std_ulogic; + rgmii_eth_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_eth_tx_ctl : out std_ulogic; + rgmii_eth_tx_data : out std_ulogic_vector(3 downto 0); + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic; + interrupt : out std_ulogic + ); + end component; + + signal wb_eth_cyc : std_ulogic; + signal wb_eth_adr : std_ulogic_vector(29 downto 0); + + begin + liteeth : liteeth_core + port map( + sys_clock => system_clk, + sys_reset => soc_rst, + rgmii_eth_clocks_tx => eth_clocks_tx, + rgmii_eth_clocks_rx => eth_clocks_rx, + rgmii_eth_rst_n => eth_rst_n, + rgmii_eth_int_n => eth_int_n, + rgmii_eth_mdio => eth_mdio, + rgmii_eth_mdc => eth_mdc, + rgmii_eth_rx_ctl => eth_rx_ctl, + rgmii_eth_rx_data => eth_rx_data, + rgmii_eth_tx_ctl => eth_tx_ctl, + rgmii_eth_tx_data => eth_tx_data, + wishbone_adr => wb_eth_adr, + wishbone_dat_w => wb_ext_io_in.dat, + wishbone_dat_r => wb_eth_out.dat, + wishbone_sel => wb_ext_io_in.sel, + wishbone_cyc => wb_eth_cyc, + wishbone_stb => wb_ext_io_in.stb, + wishbone_ack => wb_eth_out.ack, + wishbone_we => wb_ext_io_in.we, + wishbone_cti => "000", + wishbone_bte => "00", + wishbone_err => open, + interrupt => ext_irq_eth + ); + + -- Gate cyc with "chip select" from soc + wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; + + -- Remove top address bits as liteeth decoder doesn't know about them + wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0); + + -- LiteETH isn't pipelined + wb_eth_out.stall <= not wb_eth_out.ack; + + end generate; + + no_liteeth : if not USE_LITEETH generate + ext_irq_eth <= '0'; + end generate; + + + -- Mux WB response on the IO bus + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_dram_ctrl_out; wb_sdcard_out.ack <= '0'; wb_sdcard_out.stall <= '0'; - ext_irq_eth <= '0'; ext_irq_sdcard <= '0'; ext_rst_n <= '1'; diff --git a/microwatt.core b/microwatt.core index a379444..b14a61e 100644 --- a/microwatt.core +++ b/microwatt.core @@ -355,11 +355,12 @@ targets: antmicro-artix-dc-scm: default_tool: vivado - filesets: [core, antmicro-artix-dc-scm, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific] + filesets: [core, antmicro-artix-dc-scm, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific] parameters : - memory_size - ram_init_file - use_litedram=true + - use_liteeth=true - clk_input - clk_frequency - disable_flatten_core @@ -369,7 +370,7 @@ targets: - has_uart1 - has_fpu - has_btc - generate: [litedram_nexys_video, git_hash] + generate: [litedram_nexys_video, liteeth_nexys_video, git_hash] tools: vivado: {part : xc7a100tfgg484-1} toplevel : toplevel