From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Aug 2020 14:01:23 +0000 (+0100)
Subject: oink, write_cr shiftrot record width was zero (??)
X-Git-Tag: semi_working_ecp5~250^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13c6fee48e13403afcabe442738b71e45d51214a;p=soc.git

oink, write_cr shiftrot record width was zero (??)
---

diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py
index 2eb052d3..67b351f6 100644
--- a/src/soc/fu/shift_rot/sr_input_record.py
+++ b/src/soc/fu/shift_rot/sr_input_record.py
@@ -17,7 +17,7 @@ class CompSROpSubset(CompOpSubsetBase):
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
-                  ('write_cr0', 0),
+                  ('write_cr0', 1),
                   ('input_carry', CryIn),
                   ('output_carry', 1),
                   ('input_cr', 1),