From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 29 Jul 2022 09:27:30 +0000 (-0700)
Subject: format table
X-Git-Tag: opf_rfc_ls005_v1~952
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13c7963d8ee00b4b448add28d4d9fee9924c63ff;p=libreriscv.git

format table
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 4cc7aeb80..67b066be6 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,14 +1,14 @@
 **ISA Comparison Table** - discussion and research at <https://bugs.libre-soc.org/show_bug.cgi?id=893>
 
-|ISA <br>name  |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint  |LDST <br> Fault-First|Data-dep<br> Fail-first|Pred-<br> Result|Matrix HW<br> support|DCT/FFT HW<br> support |
-|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|-----------------------|----------------|---------------------|-----------------------|
-|Draft SVP64   |5 [^svp64_prefix]          |see [^svp64_intrin_cnt]          |Scalable [^svp64_scalable]         |yes                |yes                 |yes [^twin_pred]              |no [^svp64_no_vec_regs]                   |see [^svp64_128]         |yes [^bigint] |yes [^fail_first]              |yes [^data_fail_first]                |yes [^pred_result]         |yes [^svp64_mat]             | yes[^svp64_fft]               |
-|VSX           |700+           |700+? [^vsx_intrin]        |Packed SIMD          |no                 |no                  |no                   |yes [^vsx_vec_regs]                 |yes             |no      |no                   |no                     |no              |yes [^ppc_mma]             | no                    |
-|NEON          |~250 [^neon_opcodes]      |7088 [^neon_intrin]         |Packed SIMD          |no                 |no                  |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   | no                    |
-|SVE2          |~1000 [^sve2_opcodes]     |6040 [^sve2_intrin]         |Predicated SIMD[^sve2_no_setvl]  |no [^sve2_no_setvl]            |yes                 |no                   |yes                      |yes             |no      |yes [^fail_first]              |no                     |no              |yes [^sve2_mat]             | no                    |
-|AVX512 [^avx512_wikipedia]   |~1000s [^avx512_opcodes]    |7256 [^avx512_intrin]         |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes             |no      |no                   |no                     |no              |yes [^x86_amx]             | no                    |
-|RVV [^rvv_spec]      |~190 [^rvv_opcodes]      |~25000 [^rvv_intrin]       |Scalable [^rvv_scalable]        |yes                |yes                 |no                   |yes                      |yes [^rvv_128]        |no      |yes                  |no                     |no              |no                   | no                    |
-|Aurora SX[^sx_aurora] |~200 [^aurora_isa]      |unknown [^aurora_intrin]      |Scalable [^aurora_scalable]        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                     |no              |?                    | no                    |
+|ISA <br>name              |Num <br>opcodes         |Num <br>intrinsics      |Taxonomy / <br> Class          |setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint       |LDST <br> Fault-First|Data-dep<br> Fail-first|Pred-<br> Result  |Matrix HW<br> support|DCT/FFT HW<br> support |
+|--------------------------|------------------------|------------------------|-------------------------------|-------------------|--------------------|---------------------|-------------------------|----------------|-------------|---------------------|-----------------------|------------------|---------------------|-----------------------|
+|Draft SVP64               |5 [^svp64_prefix]       |see [^svp64_intrin_cnt] |Scalable [^svp64_scalable]     |yes                |yes                 |yes [^twin_pred]     |no [^svp64_no_vec_regs]  |see [^svp64_128]|yes [^bigint]|yes [^fail_first]    |yes [^data_fail_first] |yes [^pred_result]|yes [^svp64_mat]     | yes[^svp64_fft]       |
+|VSX                       |700+                    |700+? [^vsx_intrin]     |Packed SIMD                    |no                 |no                  |no                   |yes [^vsx_vec_regs]      |yes             |no           |no                   |no                     |no                |yes [^ppc_mma]       | no                    |
+|NEON                      |~250 [^neon_opcodes]    |7088 [^neon_intrin]     |Packed SIMD                    |no                 |no                  |no                   |yes                      |yes             |no           |no                   |no                     |no                |no                   | no                    |
+|SVE2                      |~1000 [^sve2_opcodes]   |6040 [^sve2_intrin]     |Predicated SIMD[^sve2_no_setvl]|no [^sve2_no_setvl]|yes                 |no                   |yes                      |yes             |no           |yes [^fail_first]    |no                     |no                |yes [^sve2_mat]      | no                    |
+|AVX512 [^avx512_wikipedia]|~1000s [^avx512_opcodes]|7256 [^avx512_intrin]   |Predicated SIMD                |no                 |yes                 |no                   |yes                      |yes             |no           |no                   |no                     |no                |yes [^x86_amx]       | no                    |
+|RVV [^rvv_spec]           |~190 [^rvv_opcodes]     |~25000 [^rvv_intrin]    |Scalable [^rvv_scalable]       |yes                |yes                 |no                   |yes                      |yes [^rvv_128]  |no           |yes                  |no                     |no                |no                   | no                    |
+|Aurora SX[^sx_aurora]     |~200 [^aurora_isa]      |unknown [^aurora_intrin]|Scalable [^aurora_scalable]    |yes                |yes                 |no                   |yes                      |no              |no           |no                   |no                     |no                |?                    | no                    |
 
 [^svp64_prefix]: plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
 [^svp64_scalable]: A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]