From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 4 Apr 2023 04:59:15 +0000 (-0700)
Subject: re-narrow fcvttg asm alias table
X-Git-Tag: opf_rfc_ls012_v1~132
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13c991caadcc5e59f394a494c3e3d68fa483f4ff;p=libreriscv.git

re-narrow fcvttg asm alias table
---

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 390382e1f..05fe8343b 100644
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -681,18 +681,24 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-TODO narrow table
-
-| Assembly Alias            | Full Instruction           | Assembly Alias            | Full Instruction           |
-|---------------------------|----------------------------|---------------------------|----------------------------|
-| `fcvttgw RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 0`   | `fcvttgd RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 2`   |
-| `fcvttgw. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 0`  | `fcvttgd. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 2`  |
-| `fcvttgwo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 0`  | `fcvttgdo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 2`  |
-| `fcvttgwo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 0` | `fcvttgdo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 2` |
-| `fcvttguw RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 1`   | `fcvttgud RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 3`   |
-| `fcvttguw. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 1`  | `fcvttgud. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 3`  |
-| `fcvttguwo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 1`  | `fcvttgudo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 3`  |
-| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` | `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
+| Assembly Alias            | Full Instruction           |
+|---------------------------|----------------------------|
+| `fcvttgw RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 0`   |
+| `fcvttgw. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 0`  |
+| `fcvttgwo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 0`  |
+| `fcvttgwo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 0` |
+| `fcvttguw RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 1`   |
+| `fcvttguw. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 1`  |
+| `fcvttguwo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 1`  |
+| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` |
+| `fcvttgd RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 2`   |
+| `fcvttgd. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 2`  |
+| `fcvttgdo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 2`  |
+| `fcvttgdo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 2` |
+| `fcvttgud RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 3`   |
+| `fcvttgud. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 3`  |
+| `fcvttgudo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 3`  |
+| `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
 
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