From: H.J. Lu <hongjiu.lu@intel.com>
Date: Fri, 19 Oct 2018 09:13:34 +0000 (+0000)
Subject: i386: Enable AVX512 memory broadcast for FP add
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13e29c36489a9e4f923f4d8194a50d395ff5deaa;p=gcc.git

i386: Enable AVX512 memory broadcast for FP add

Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for FP add operations.

gcc/

	PR target/72782
	* config/i386/sse.md
	(*<plusminus_insn><mode>3<mask_name>_bcst_1): New.
	(*add<mode>3<mask_name>_bcst_2): Likewise.

gcc/testsuite/

	PR target/72782
	* gcc.target/i386/avx512-binop-1.h: New file.
	* gcc.target/i386/avx512-binop-2.h: Likewise.
	* gcc.target/i386/avx512-binop-3.h: Likewise.
	* gcc.target/i386/avx512-binop-4.h: Likewise.
	* gcc.target/i386/avx512-binop-5.h: Likewise.
	* gcc.target/i386/avx512-binop-6.h: Likewise.
	* gcc.target/i386/avx512f-add-df-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-2.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-3.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-4.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-5.c: Likewise.
	* gcc.target/i386/avx512f-add-sf-zmm-6.c: Likewise.
	* gcc.target/i386/avx512f-sub-df-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-sub-sf-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-sub-sf-zmm-2.c: Likewise.
	* gcc.target/i386/avx512f-sub-sf-zmm-3.c: Likewise.
	* gcc.target/i386/avx512f-sub-sf-zmm-4.c: Likewise.
	* gcc.target/i386/avx512f-sub-sf-zmm-5.c: Likewise.
	* gcc.target/i386/avx512vl-add-sf-xmm-1.c: Likewise.
	* gcc.target/i386/avx512vl-add-sf-ymm-1.c: Likewise.
	* gcc.target/i386/avx512vl-sub-sf-xmm-1.c: Likewise.
	* gcc.target/i386/avx512vl-sub-sf-ymm-1.c: Likewise.

From-SVN: r265311
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ee08f80154c..50f8d785911 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* config/i386/sse.md
+	(*<plusminus_insn><mode>3<mask_name>_bcst_1): New.
+	(*add<mode>3<mask_name>_bcst_2): Likewise.
+
 2018-10-19  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/i386/sse.md
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 06144dc4662..411c78ae8d3 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1684,6 +1684,34 @@
    (set_attr "prefix" "<mask_prefix3>")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*<plusminus_insn><mode>3<mask_name>_bcst_1"
+  [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
+	(plusminus:VF_AVX512
+	  (match_operand:VF_AVX512 1 "register_operand" "v")
+	  (vec_duplicate:VF_AVX512
+	    (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+  "TARGET_AVX512F
+   && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
+   && <mask_mode512bit_condition>"
+  "v<plusminus_mnemonic><ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<avx512bcst>}"
+  [(set_attr "prefix" "evex")
+   (set_attr "type" "sseadd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*add<mode>3<mask_name>_bcst_2"
+  [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
+	(plus:VF_AVX512
+	  (vec_duplicate:VF_AVX512
+	    (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
+	  (match_operand:VF_AVX512 2 "register_operand" "v")))]
+  "TARGET_AVX512F
+   && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
+   && <mask_mode512bit_condition>"
+  "vadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
+  [(set_attr "prefix" "evex")
+   (set_attr "type" "sseadd")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "<sse>_vm<plusminus_insn><mode>3<mask_scalar_name><round_scalar_name>"
   [(set (match_operand:VF_128 0 "register_operand" "=x,v")
 	(vec_merge:VF_128
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 705d745a2d4..5f216f05425 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,30 @@
+2018-10-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* gcc.target/i386/avx512-binop-1.h: New file.
+	* gcc.target/i386/avx512-binop-2.h: Likewise.
+	* gcc.target/i386/avx512-binop-3.h: Likewise.
+	* gcc.target/i386/avx512-binop-4.h: Likewise.
+	* gcc.target/i386/avx512-binop-5.h: Likewise.
+	* gcc.target/i386/avx512-binop-6.h: Likewise.
+	* gcc.target/i386/avx512f-add-df-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-2.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-3.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-4.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-5.c: Likewise.
+	* gcc.target/i386/avx512f-add-sf-zmm-6.c: Likewise.
+	* gcc.target/i386/avx512f-sub-df-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-sub-sf-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-sub-sf-zmm-2.c: Likewise.
+	* gcc.target/i386/avx512f-sub-sf-zmm-3.c: Likewise.
+	* gcc.target/i386/avx512f-sub-sf-zmm-4.c: Likewise.
+	* gcc.target/i386/avx512f-sub-sf-zmm-5.c: Likewise.
+	* gcc.target/i386/avx512vl-add-sf-xmm-1.c: Likewise.
+	* gcc.target/i386/avx512vl-add-sf-ymm-1.c: Likewise.
+	* gcc.target/i386/avx512vl-sub-sf-xmm-1.c: Likewise.
+	* gcc.target/i386/avx512vl-sub-sf-ymm-1.c: Likewise.
+
 2018-10-19  Ilya Leoshkevich  <iii@linux.ibm.com>
 
 	PR rtl-optimization/87596
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-1.h b/gcc/testsuite/gcc.target/i386/avx512-binop-1.h
new file mode 100644
index 00000000000..5bfacd3007e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-1.h
@@ -0,0 +1,12 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+type
+foo (type x, SCALAR *f)
+{
+  return OP (vec, op, suffix) (x , DUP (vec, suffix, *f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-2.h b/gcc/testsuite/gcc.target/i386/avx512-binop-2.h
new file mode 100644
index 00000000000..2e02ede6f11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-2.h
@@ -0,0 +1,12 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+type
+foo (type x, SCALAR *f)
+{
+  return OP (vec, op, suffix) (DUP (vec, suffix, *f), x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-3.h b/gcc/testsuite/gcc.target/i386/avx512-binop-3.h
new file mode 100644
index 00000000000..b1b7e88176d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-3.h
@@ -0,0 +1,15 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+extern SCALAR bar (void);
+
+type
+foo (type x)
+{
+  SCALAR f = bar ();
+  return OP (vec, op, suffix) (DUP (vec, suffix, f), x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-4.h b/gcc/testsuite/gcc.target/i386/avx512-binop-4.h
new file mode 100644
index 00000000000..4cf408887e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-4.h
@@ -0,0 +1,12 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+type
+foo (type x, SCALAR f)
+{
+  return OP (vec, op, suffix) (DUP (vec, suffix, f), x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-5.h b/gcc/testsuite/gcc.target/i386/avx512-binop-5.h
new file mode 100644
index 00000000000..dd59a332da0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-5.h
@@ -0,0 +1,14 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+extern SCALAR f;
+
+type
+foo (type x)
+{
+  return OP (vec, op, suffix) (x , DUP (vec, suffix, f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512-binop-6.h b/gcc/testsuite/gcc.target/i386/avx512-binop-6.h
new file mode 100644
index 00000000000..9e4afc9b4e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512-binop-6.h
@@ -0,0 +1,14 @@
+#include <immintrin.h>
+
+#define PASTER2(x,y)		x##y
+#define PASTER3(x,y,z)		_mm##x##_##y##_##z
+#define OP(vec, op, suffix)	PASTER3 (vec, op, suffix)
+#define DUP(vec, suffix, val)	PASTER3 (vec, set1, suffix) (val)
+
+extern SCALAR f;
+
+type
+foo (type x)
+{
+  return OP (vec, op, suffix) (DUP (vec, suffix, f), x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-df-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-df-zmm-1.c
new file mode 100644
index 00000000000..d2f66517f8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-df-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastsd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512d
+#define vec 512
+#define op add
+#define suffix pd
+#define SCALAR double
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-1.c
new file mode 100644
index 00000000000..b664ea9d916
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-2.c
new file mode 100644
index 00000000000..a2da3064344
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-3.c
new file mode 100644
index 00000000000..163da1f10ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vaddps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-4.c
new file mode 100644
index 00000000000..8d46cfba6f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-5.c
new file mode 100644
index 00000000000..7ba296bec1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-6.c
new file mode 100644
index 00000000000..42b05aa0ca8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-sf-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-df-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-df-zmm-1.c
new file mode 100644
index 00000000000..39d668d6514
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-df-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastsd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512d
+#define vec 512
+#define op sub
+#define suffix pd
+#define SCALAR double
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-1.c
new file mode 100644
index 00000000000..4dfb3b94d5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-2.c
new file mode 100644
index 00000000000..28b4b4d76a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-3.c
new file mode 100644
index 00000000000..62d305822eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-4.c
new file mode 100644
index 00000000000..f546986333a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-5.c
new file mode 100644
index 00000000000..148873e1ed8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-sf-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-xmm-1.c
new file mode 100644
index 00000000000..86f37e77479
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfma -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128
+#define vec
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-ymm-1.c
new file mode 100644
index 00000000000..7e00bc8f7f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-sf-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfma -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256
+#define vec 256
+#define op add
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-xmm-1.c
new file mode 100644
index 00000000000..7228e07e1e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfma -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128
+#define vec
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-ymm-1.c
new file mode 100644
index 00000000000..93c53624989
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-sf-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfma -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256
+#define vec 256
+#define op sub
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"