From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 19:50:30 +0000 (-0700)
Subject: Update CHANGELOG
X-Git-Tag: working-ls180~1208^2~158
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13e2e8df11b4af9ce5512508caad793c659b9479;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index e74af6b65..13cfb812b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,12 +17,13 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
+    - Added "shregmap -tech xilinx"
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
-    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
-    - "synth_xilinx" to now infer wide multiplexers
+    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
+    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
 
 
 Yosys 0.7 .. Yosys 0.8