From: Eric Botcazou <ebotcazou@adacore.com>
Date: Fri, 2 Aug 2013 21:41:58 +0000 (+0000)
Subject: sparc.c (sparc_emit_membar_for_model): Add the implied StoreLoad barrier for atomic... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13ec0527eae61e42c9b0356a9752d6fa4702c2c3;p=gcc.git

sparc.c (sparc_emit_membar_for_model): Add the implied StoreLoad barrier for atomic operations if before.

	* config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
	the implied StoreLoad barrier for atomic operations if before.

From-SVN: r201450
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e0e253745f..85ef86bc594 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-08-02  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/sparc/sparc.c (sparc_emit_membar_for_model) <SMM_TSO>: Add
+	the implied StoreLoad barrier for atomic operations if before.
+
 2013-08-02  Jan Hubicka  <jh@suse.cz>
 	    Martin Liska  <marxin.liska@gmail.com>
 
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 48c25dcd5cd..87cfacaa72c 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -11318,6 +11318,11 @@ sparc_emit_membar_for_model (enum memmodel model,
       /* Total Store Ordering: all memory transactions with store semantics
 	 are followed by an implied StoreStore.  */
       implied |= StoreStore;
+
+      /* If we're not looking for a raw barrer (before+after), then atomic
+	 operations get the benefit of being both load and store.  */
+      if (load_store == 3 && before_after == 1)
+	implied |= StoreLoad;
       /* FALLTHRU */
 
     case SMM_PSO: