From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 Aug 2020 23:19:34 +0000 (+0100)
Subject: divide logical pipe into 2 (simple phase last)
X-Git-Tag: semi_working_ecp5~360
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13ef0d193633f20668004eae496d9078de8a95b5;p=soc.git

divide logical pipe into 2 (simple phase last)
---

diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py
index 41aea148..a16bd78a 100644
--- a/src/soc/fu/logical/pipeline.py
+++ b/src/soc/fu/logical/pipeline.py
@@ -4,23 +4,31 @@ from soc.fu.logical.input_stage import LogicalInputStage
 from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.logical.output_stage import LogicalOutputStage
 
-class LogicalStages(PipeModBaseChain):
+
+class LogicalStages1(PipeModBaseChain):
     def get_chain(self):
         inp = LogicalInputStage(self.pspec)
         main = LogicalMainStage(self.pspec)
+        return [inp, main]
+
+
+class LogicalStages2(PipeModBaseChain):
+    def get_chain(self):
         out = LogicalOutputStage(self.pspec)
-        return [inp, main, out]
+        return [out]
 
 
 class LogicalBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
         self.pspec = pspec
-        self.pipe1 = LogicalStages(pspec)
-        self._eqs = self.connect([self.pipe1])
+        self.pipe1 = LogicalStages1(pspec)
+        self.pipe2 = LogicalStages2(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.logical_pipe1 = self.pipe1
+        m.submodules.logical_pipe2 = self.pipe2
         m.d.comb += self._eqs
         return m
diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 26ef54e6..725cf306 100644
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -161,7 +161,6 @@ class TestRunner(FHDLTestCase):
         m.submodules.alu = alu = LogicalBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
-        comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -193,7 +192,12 @@ class TestRunner(FHDLTestCase):
                     fn_unit = yield pdecode2.e.do.fn_unit
                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
                     yield from set_alu_inputs(alu, pdecode2, simulator)
+
+                    # set valid for one cycle, propagate through pipeline...
+                    yield alu.p.valid_i.eq(1)
                     yield
+                    yield alu.p.valid_i.eq(0)
+
                     opname = code.split(' ')[0]
                     yield from simulator.call(opname)
                     index = simulator.pc.CIA.value//4
@@ -206,6 +210,8 @@ class TestRunner(FHDLTestCase):
 
                     yield from self.check_alu_outputs(alu, pdecode2,
                                                       simulator, code)
+                    yield Settle()
+
 
         sim.add_sync_process(process)
         with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw",