From: Nathan Binkert Date: Tue, 13 Jul 2004 02:58:22 +0000 (-0400) Subject: make the cache access latency a parameter that is based on bus X-Git-Tag: m5_1.0_tutorial~244 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13f8dc981fc898e6e200689d305b39f0718f8c83;p=gem5.git make the cache access latency a parameter that is based on bus ticks for the most commonly accessed devices. dev/baddev.cc: Get rid of the constant cache access latency. For unimportant devices, don't add any latency. dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ns_gige.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart.cc: dev/uart.hh: make the cache access latency a parameter that is based on bus ticks. dev/io_device.cc: dev/io_device.hh: add an io latency variable dev/ns_gige.hh: this moved to io_device.hh --HG-- extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789 --- diff --git a/dev/baddev.cc b/dev/baddev.cc index 8b552e989..7c563e80a 100644 --- a/dev/baddev.cc +++ b/dev/baddev.cc @@ -78,7 +78,7 @@ BadDevice::write(MemReqPtr &req, const uint8_t *data) Tick BadDevice::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick; } BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice) @@ -103,7 +103,8 @@ END_INIT_SIM_OBJECT_PARAMS(BadDevice) CREATE_SIM_OBJECT(BadDevice) { - return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, devicename); + return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, + devicename); } REGISTER_SIM_OBJECT("BadDevice", BadDevice) diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 4805570d2..e40248461 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -60,7 +60,7 @@ IdeController::IdeController(const string &name, IntrControl *ic, MemoryController *mmu, PciConfigAll *cf, PciConfigData *cd, Tsunami *t, uint32_t bus_num, uint32_t dev_num, uint32_t func_num, - Bus *host_bus, HierParams *hier) + Bus *host_bus, Tick pio_latency, HierParams *hier) : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t) { // put back pointer into Tsunami @@ -105,6 +105,7 @@ IdeController::IdeController(const string &name, IntrControl *ic, dmaInterface = new DMAInterface(name + ".dma", host_bus, host_bus, 1); + pioLatency = pio_latency * host_bus->clockRatio; } // setup the disks attached to controller @@ -261,7 +262,7 @@ Tick IdeController::cacheAccess(MemReqPtr &req) { // @todo Add more accurate timing to cache access - return curTick + 1000; + return curTick + pioLatency; } //// @@ -700,6 +701,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) Param pci_dev; Param pci_func; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(IdeController) @@ -716,6 +718,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(IdeController) @@ -724,7 +727,7 @@ CREATE_SIM_OBJECT(IdeController) { return new IdeController(getInstanceName(), intr_ctrl, disks, mmu, configspace, configdata, tsunami, pci_bus, - pci_dev, pci_func, io_bus, hier); + pci_dev, pci_func, io_bus, pio_latency, hier); } REGISTER_SIM_OBJECT("IdeController", IdeController) diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index 39c64eb30..b29e5ae9a 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -167,7 +167,7 @@ class IdeController : public PciDev MemoryController *mmu, PciConfigAll *cf, PciConfigData *cd, Tsunami *t, uint32_t bus_num, uint32_t dev_num, uint32_t func_num, - Bus *host_bus, HierParams *hier); + Bus *host_bus, Tick pio_latency, HierParams *hier); /** * Deletes the connected devices. diff --git a/dev/io_device.cc b/dev/io_device.cc index b39efa1f5..7703ad5e3 100644 --- a/dev/io_device.cc +++ b/dev/io_device.cc @@ -32,7 +32,7 @@ #include "sim/builder.hh" PioDevice::PioDevice(const std::string &name) - : FunctionalMemory(name), pioInterface(NULL) + : FunctionalMemory(name), pioInterface(NULL), pioLatency(0) {} PioDevice::~PioDevice() diff --git a/dev/io_device.hh b/dev/io_device.hh index e6014e73d..f49afc0a6 100644 --- a/dev/io_device.hh +++ b/dev/io_device.hh @@ -40,6 +40,7 @@ class PioDevice : public FunctionalMemory { protected: BaseInterface *pioInterface; + Tick pioLatency; public: PioDevice(const std::string &name); diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 74ace9d99..ff0c90f15 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -120,7 +120,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, acceptMulticast(false), acceptUnicast(false), acceptPerfect(false), acceptArp(false), physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false), - intrEvent(0), interface(0), pioLatency(pio_latency) + intrEvent(0), interface(0) { tsunami->ethernet = this; @@ -128,6 +128,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, pioInterface = newPioInterface(name, hier, header_bus, this, &NSGigE::cacheAccess); + pioLatency = pio_latency * header_bus->clockRatio; + if (payload_bus) dmaInterface = new DMAInterface(name + ".dma", header_bus, payload_bus, 1); @@ -138,9 +140,10 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, pioInterface = newPioInterface(name, hier, payload_bus, this, &NSGigE::cacheAccess); + pioLatency = pio_latency * payload_bus->clockRatio; + dmaInterface = new DMAInterface(name + ".dma", payload_bus, payload_bus, 1); - } @@ -2659,7 +2662,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM_DFLT(header_bus, "The IO Bus to attach to for headers", NULL), INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(dma_desc_free, "DMA of Descriptors is free", false), INIT_PARAM_DFLT(dma_data_free, "DMA of Data is free", false), INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0), diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 55cc92a2c..79ae00e64 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -383,9 +383,6 @@ class NSGigE : public PciDev Stats::Formula txPacketRate; Stats::Formula rxPacketRate; - private: - Tick pioLatency; - public: Tick cacheAccess(MemReqPtr &req); }; diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 8937b8e67..740a9b4ac 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -47,7 +47,7 @@ using namespace std; PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *bus) + HierParams *hier, Bus *bus, Tick pio_latency) : PioDevice(name), addr(a) { mmu->add_child(this, Range(addr, addr + size)); @@ -56,6 +56,7 @@ PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu, pioInterface = newPioInterface(name, hier, bus, this, &PciConfigAll::cacheAccess); pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } // Make all the pointers to devices null @@ -175,7 +176,7 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion) Tick PciConfigAll::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -186,6 +187,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll) Param addr; Param mask; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll) @@ -196,13 +198,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll) INIT_PARAM(addr, "Device Address"), INIT_PARAM(mask, "Address Mask"), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(PciConfigAll) CREATE_SIM_OBJECT(PciConfigAll) { - return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus); + return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus, + pio_latency); } REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll) diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh index 356e62a3c..d6b37b9b1 100644 --- a/dev/pciconfigall.hh +++ b/dev/pciconfigall.hh @@ -73,7 +73,7 @@ class PciConfigAll : public PioDevice * @param bus The bus that this device is attached to */ PciConfigAll(const std::string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *bus); + HierParams *hier, Bus *bus, Tick pio_latency); /** diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 0fbfcb56f..870924a2f 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -49,7 +49,8 @@ using namespace std; TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus* bus) + MemoryController *mmu, HierParams *hier, Bus* bus, + Tick pio_latency) : PioDevice(name), addr(a), tsunami(t) { mmu->add_child(this, Range(addr, addr + size)); @@ -66,6 +67,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiCChip::cacheAccess); pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } drir = 0; @@ -383,7 +385,7 @@ TsunamiCChip::clearDRIR(uint32_t interrupt) Tick TsunamiCChip::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } @@ -417,6 +419,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) SimObjectParam mmu; Param addr; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) @@ -427,13 +430,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) INIT_PARAM(mmu, "Memory Controller"), INIT_PARAM(addr, "Device Address"), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) CREATE_SIM_OBJECT(TsunamiCChip) { - return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus); + return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, + io_bus, pio_latency); } REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index a358c98ba..3269cf53a 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -100,7 +100,8 @@ class TsunamiCChip : public PioDevice * @param bus The bus that this device is attached to */ TsunamiCChip(const std::string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus *bus); + MemoryController *mmu, HierParams *hier, Bus *bus, + Tick pio_latency); /** * Process a read to the CChip. diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index 4c798a852..105e3b5b7 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -160,7 +160,8 @@ TsunamiIO::ClockEvent::unserialize(Checkpoint *cp, const std::string §ion) } TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, - Addr a, MemoryController *mmu, HierParams *hier, Bus *bus) + Addr a, MemoryController *mmu, HierParams *hier, Bus *bus, + Tick pio_latency) : PioDevice(name), addr(a), tsunami(t), rtc(t) { mmu->add_child(this, Range(addr, addr + size)); @@ -169,6 +170,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiIO::cacheAccess); pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } // set the back pointer from tsunami to myself @@ -425,7 +427,7 @@ TsunamiIO::clearPIC(uint8_t bitvector) Tick TsunamiIO::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } void @@ -476,6 +478,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) SimObjectParam mmu; Param addr; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) @@ -488,6 +491,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO) INIT_PARAM(mmu, "Memory Controller"), INIT_PARAM(addr, "Device Address"), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(TsunamiIO) @@ -495,7 +499,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiIO) CREATE_SIM_OBJECT(TsunamiIO) { return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier, - io_bus); + io_bus, pio_latency); } REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO) diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh index 75e5d764c..d507355c3 100644 --- a/dev/tsunami_io.hh +++ b/dev/tsunami_io.hh @@ -237,7 +237,8 @@ class TsunamiIO : public PioDevice * @param mmu pointer to the memory controller that sends us events. */ TsunamiIO(const std::string &name, Tsunami *t, time_t init_time, - Addr a, MemoryController *mmu, HierParams *hier, Bus *bus); + Addr a, MemoryController *mmu, HierParams *hier, Bus *bus, + Tick pio_latency); /** * Create the tm struct from seconds since 1970 diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index b1346bb1a..89940fb5a 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -50,7 +50,7 @@ using namespace std; TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, MemoryController *mmu, HierParams *hier, - Bus *bus) + Bus *bus, Tick pio_latency) : PioDevice(name), addr(a), tsunami(t) { mmu->add_child(this, Range(addr, addr + size)); @@ -65,6 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiPChip::cacheAccess); pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } @@ -351,7 +352,7 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) Tick TsunamiPChip::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) @@ -360,6 +361,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) SimObjectParam mmu; Param addr; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) @@ -370,13 +372,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) INIT_PARAM(mmu, "Memory Controller"), INIT_PARAM(addr, "Device Address"), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) CREATE_SIM_OBJECT(TsunamiPChip) { - return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus); + return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, + io_bus, pio_latency); } REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh index af50872a0..f88098d58 100644 --- a/dev/tsunami_pchip.hh +++ b/dev/tsunami_pchip.hh @@ -80,7 +80,8 @@ class TsunamiPChip : public PioDevice * @param bus The bus that this device is attached to */ TsunamiPChip(const std::string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus *bus); + MemoryController *mmu, HierParams *hier, Bus *bus, + Tick pio_latency); /** * Translate a PCI bus address to a memory address for DMA. diff --git a/dev/uart.cc b/dev/uart.cc index 4784ad640..8ba59579d 100644 --- a/dev/uart.cc +++ b/dev/uart.cc @@ -88,7 +88,7 @@ Uart::IntrEvent::scheduleIntr() } Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a, - Addr s, HierParams *hier, Bus *bus, Platform *p) + Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p) : PioDevice(name), addr(a), size(s), cons(c), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT), platform(p) { @@ -98,7 +98,8 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a, if (bus) { pioInterface = newPioInterface(name, hier, bus, this, &Uart::cacheAccess); - pioInterface->addAddrRange(addr, addr + size - 1); + pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } readAddr = 0; @@ -370,7 +371,7 @@ Uart::dataAvailable() Tick Uart::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } void @@ -432,6 +433,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart) Param addr; Param size; SimObjectParam io_bus; + Param pio_latency; SimObjectParam hier; @@ -445,6 +447,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Uart) INIT_PARAM(addr, "Device Address"), INIT_PARAM_DFLT(size, "Device size", 0x8), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(Uart) @@ -452,7 +455,7 @@ END_INIT_SIM_OBJECT_PARAMS(Uart) CREATE_SIM_OBJECT(Uart) { return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus, - platform); + pio_latency, platform); } REGISTER_SIM_OBJECT("Uart", Uart) diff --git a/dev/uart.hh b/dev/uart.hh index 07ad4d0c8..ac8ed7d73 100644 --- a/dev/uart.hh +++ b/dev/uart.hh @@ -76,7 +76,8 @@ class Uart : public PioDevice public: Uart(const string &name, SimConsole *c, MemoryController *mmu, - Addr a, Addr s, HierParams *hier, Bus *bus, Platform *p); + Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency, + Platform *p); Fault read(MemReqPtr &req, uint8_t *data); Fault write(MemReqPtr &req, const uint8_t *data);