From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Apr 2019 23:05:24 +0000 (-0700)
Subject: Undo #895 by instead setting an attribute
X-Git-Tag: yosys-0.9~171^2~13^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=13fc70d7a44965fc87aa76682b32d4961efb093d;p=yosys.git

Undo #895 by instead setting an attribute
---

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index bac2dc2cd..6ac59bfb2 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -360,23 +360,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
 			}
 		}
 
-		// Transform into a $shiftx where possible
-		if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux") {
-			// Create bit-blasted $shiftx-es that shifts by the address line used in the case statement
-			auto pmux_b_port = last_mux_cell->getPort("\\B");
-			auto pmux_y_port = last_mux_cell->getPort("\\Y");
-			int width = last_mux_cell->getParam("\\WIDTH").as_int();
-			for (int i = 0; i < width; ++i) {
-				RTLIL::SigSpec a_port;
-				// Because we went in reverse order above, un-reverse $pmux's B port here
-				for (int j = pmux_b_port.size()/width-1; j >= 0; --j)
-					a_port.append(pmux_b_port.extract(j*width+i, 1));
-				// Create a $shiftx that shifts by the address line used in the case statement
-				mod->addShiftx(NEW_ID, a_port, sw->signal, pmux_y_port.extract(i, 1));
-			}
-			// Disconnect $pmux by replacing its output port with a floating wire
-			last_mux_cell->setPort("\\Y", mod->addWire(NEW_ID, width));
-		}
+		// Mark this pmux as being $shiftx compatible
+		if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux")
+			last_mux_cell->set_bool_attribute("\\shiftx_compatible");
 	}
 
 	return result;