From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 05:02:59 +0000 (+0100)
Subject: add shiftleft and lessthan
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14023cdfaa4760ffc93aaaedef73fd3d7233245d;p=riscv-isa-sim.git

add shiftleft and lessthan
---

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 7db7613..9b09d6e 100644
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1 @@
-WRITE_RD(sext_xlen(RS1 << (RS2 & (xlen-1))));
+WRITE_RD(sext_xlen(rv_sl(RS1, (RS2 & (xlen-1)))));
diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 26782fd..156d4e3 100644
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,2 @@
 require(SHAMT < xlen);
-WRITE_RD(sext_xlen(RS1 << SHAMT));
+WRITE_RD(sext_xlen(rv_sl(RS1, SHAMT)));
diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index c1fda65..c9495ab 100644
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(RS1 << SHAMT));
+WRITE_RD(sext32(rv_sl(RS1, SHAMT)));
diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index affe894..0b25be0 100644
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));
+WRITE_RD(sext32(rv_sl(RS1, (RS2 & 0x1F))));
diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 25ccd45..650d333 100644
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(RS1) < sreg_t(RS2));
+WRITE_RD(rv_lt(sreg_t(RS1), sreg_t(RS2)));
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 3671d24..216e0eb 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm()));
+WRITE_RD(rv_lt(sreg_t(RS1), sreg_t(insn.i_imm())));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index f398457..a74d2ad 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(RS1 < reg_t(insn.i_imm()));
+WRITE_RD(rv_lt(RS1, reg_t(insn.i_imm())));
diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 84d97a2..bc6e911 100644
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-WRITE_RD(RS1 < RS2);
+WRITE_RD(rv_lt(RS1, RS2));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 4f0a103..0cba560 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -267,3 +267,18 @@ reg_t sv_proc_t::rv_xor(reg_t lhs, reg_t rhs)
     return lhs ^ rhs;
 }
 
+reg_t sv_proc_t::rv_sl(reg_t lhs, reg_t rhs)
+{
+    return lhs << rhs;
+}
+
+reg_t sv_proc_t::rv_lt(reg_t lhs, reg_t rhs)
+{
+    return lhs < rhs;
+}
+
+sreg_t sv_proc_t::rv_lt(sreg_t lhs, sreg_t rhs)
+{
+    return lhs < rhs;
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 5aeccd1..b32d96f 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -104,6 +104,9 @@ public:
     reg_t rv_and(reg_t lhs, reg_t rhs);
     reg_t rv_or(reg_t lhs, reg_t rhs);
     reg_t rv_xor(reg_t lhs, reg_t rhs);
+    reg_t rv_sl(reg_t lhs, reg_t rhs);
+    reg_t rv_lt(reg_t lhs, reg_t rhs);
+    sreg_t rv_lt(sreg_t lhs, sreg_t rhs);
 
 #include "sv_insn_decl.h"
 };